JPS6234079A - Test circuit - Google Patents

Abstract

PURPOSE:To make it possible to observe the state of the arbitrary register in an integrated control apparatus and that of FF at the arbitrary point of time, by operating a counter for counting the number of elapse clocks when the integrated control apparatus is started and taking the collimation with the indication time in a register. CONSTITUTION:In order to observe the states of FFs 16, 19 of a control system at the arbitrary point of time from the outside of a chip, an observing area and an observing time are applied to a data bus terminal 2 and a register set signal is applied to a register set terminal 3 to set the area and time in a designated register 28 through an AND circuit 22. When a start signal is applied to a start signal terminal 4, the control system 15 and a counter 30 are started. A collimation circuit 31 always collimates the time parts of the counter 30 and the indication register 28 and, when collimation is taken, an integrated control apparatus is stopped and the state of the indicated area in the register 28 is taken in a buffer register 33 and the content of the buffer register 33 is outputted to the data bus terminal 2.

Description

TECHNICAL FIELD The present invention relates to a support circuit for facilitating chip testing and program debugging using a highly integrated control device.

(Conventional Technique) Conventionally, in a control device configured with SSI, MSI, etc., the contents of flip-flops and registers in the control device can be easily observed, and various tests and debugging can be easily performed.

As the control device becomes a single chip due to advances in integrated technology,
Tests at the chip level can be performed using an LSI tester without any problems.

However, various debugs in the control device cannot be discovered using an LSI tester alone; some bugs are discovered only after running an online program.

In such a case, it is impossible to use an LSI tester to observe the internal state of the control device from the outside and investigate the cause of the bug in the device, which has become a device and has complicated functions.

Additionally, for program debugging, there may be cases where it is desired to observe the contents of a register at a certain point in time, but this can be easily resolved by deploying a JKI and a console.

However, deploying a complete JKL console would be expensive, so it may only have 5TART and 5TOP functions.

(Object of the Invention) In order to solve these problems, the present invention makes it possible to observe the state of any register or flip-flop in an integrated control device at any time from outside the chip.

The drawings will be explained in detail below.

(Description of structure and operation of the invention) The figure is a block diagram of an embodiment of the invention, in which 1 to 4 are chip terminals, 1 is an address bus terminal, 2 is a data bus terminal, and 3 is a register set signal. Terminal 4 is a start signal terminal for starting the chip, 5 and 6 are output buffers, 7 to 9 are input buffers, 10 is a memory address register that holds the contents to drive the address bus,
11 is a memory buffer register that stores the contents received from the data bus, 12 is a bus for calculation, and 13 is an ALU.
(ArithIletic Logic 1Jnit)
, 14 is a buffer register for storing intermediate results of calculations;
15 is a control system that generates necessary control signals, 16.17
1 is a flip-flop, 18 is a control tree composed of flip-flops and generates a timing signal, 19 is a buffer register that stores data when driving a data bus from the processor, and 100 is an example of a well-known processor including these circuits.

20 to 25 are AND circuits, 26.27 are OR circuits, 2
8 is a designated register that stores the location and time to be observed; 2
9 is a decoder that decodes the part in the specified register 28; 29-1 to 29-n are the outputs of the decoder 29;
30 is a counter activated by the start signal terminal 4 and counts the number of elapsed clocks; 31 is a collation circuit that collates the time part of the counter 30 and the designated register 28;
2 is the output of the matching circuit 31.

The operation within the processor 100 is well known and does not require explanation, but to put it simply, the memory is accessed according to the contents of the memory address register 10, the command entered in the memory buffer register 11 is applied to the control system 15, and the control system 15 is executed. System 15 is A
It performs calculations by controlling the LU 13 and the like.

When it is desired to see the internal state of the processor 100, the location and time are applied from the outside to the data bus terminal 2 while the processor 100 is stopped, and a register set signal is applied to the register set terminal 3. As a result, the location and time are stored in the designated register 28 through the AND circuit 22.

Next, when a start signal is applied to the start signal terminal 4 to start the processor, the control system 15 is started and the counter 30 is also started.

The matching circuit 31 constantly matches the time part of the counter 30 and the designated register, and when a match occurs, outputs a logic LL 111 to the output 32 of the matching circuit.

Here, whether or not the collation circuit 31 executes the collation is determined by not collating if the time part of the designated register 28 is II O11, or by setting another collation enable/disable bit to 1 in the designated register 28.
This may be added and controlled.

When the output 32 of the verification circuit becomes logic "1", the control system 15
In addition to stopping the processor 100, the decoder 29 is enabled to decode the part in the specified register 28, and for example, the decoder output 29-n is converted into a logic I
I II II.

When the decoder output 29-n becomes logic it 1 rr,
The AND circuit 25 operates and the contents of the control tree 18 are stored in the buffer register 33. Subsequently, the AND circuit 21 operates according to the signal from the output 32 of the collation circuit, and the contents of the buffer register 33 are transferred to the data bus terminal 2. Output.

With the above configuration, it is possible to observe the state of any location in the processor at any time from the chip side.

(Description of Effects) Since the present invention has the configuration as described above,
It is possible to observe the state inside the chip without increasing the number of terminals or using an LSI tester, making it easier to analyze various bugs, and making it possible to debug programs without installing a large-scale JKL console. There are advantages to becoming

[Brief explanation of the drawing]

The figure is a block diagram of one embodiment of the present invention. 1...Address bus terminal, 2...Data bus terminal, 3...Register set signal terminal, 4...Start signal terminal, 5.6...Output buffer, 7-9...Input cover sofa , 10... Memory address register, 11... Memory buffer register, 12... Bus for calculation, 1
3...ALU, 14.19.33...Buffer register, 15...Control system, 16.17...Flip-flop. 18... Control tree, 20-25... AND circuit, 26.27... OR circuit, 28... Specification register, 29... Decoder. 29-1 to 29-n...Decoder output, 30...
Counter, 31... Verification circuit, 32... Output of the verification circuit, 100... Processor.

Claims (1)

[Claims] In an integrated control device having buses such as a data bus and an address bus, for observing the states of any registers and control flip-flops in the integrated control device at any time from outside the chip. , it has a register that specifies the location and time to observe, and information can be set in that register from outside the chip via a bus.When the integrated control device is started, a counter that counts the number of elapsed clocks operates, and the information in the register is set. When a match is made, the integrated control device is stopped, the state of the specified location in the register is loaded into a buffer register, and the contents of the buffer register are displayed outside the chip by driving a data bus. A test circuit characterized by: