JPH0357632U - - Google Patents
Info
- Publication number
- JPH0357632U JPH0357632U JP11829989U JP11829989U JPH0357632U JP H0357632 U JPH0357632 U JP H0357632U JP 11829989 U JP11829989 U JP 11829989U JP 11829989 U JP11829989 U JP 11829989U JP H0357632 U JPH0357632 U JP H0357632U
- Authority
- JP
- Japan
- Prior art keywords
- counted
- output
- predetermined
- cycle
- clock signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Measurement Of Levels Of Liquids Or Fluent Solid Materials (AREA)
- Control Of Non-Electrical Variables (AREA)
Description
第１図は、この考案の一実施例の構成を示すブ
ロツク図である。第２図は、この考案の他の実施
例の構成を示すブロツク図である。第３図は、第
１図および第２図に示すＭビツトプリスケーラ５
の動作を示したタイミングチヤートである。第４
図は、第２図の実施例において、ＰＷＭ出力のＨ
パルスおよびＬパルスの幅の設定値と、Ｍビツト
プリスケーラ５における設定値との関係を示した
タイムチヤートである。第５図は、従来のＰＷＭ
回路の一例の構成を示すブロツク図である。第６
図は、従来のＰＷＭ回路の他の例の構成を示した
ブロツク図である。第７図は、第６図に示すＰＷ
Ｍ回路の動作を示したタイムチヤートである。第
８図は、第６図に示すＰＷＭ回路の動作を示した
タイムチヤートである。
図において、１はプログラマブルのＮビツトダ
ウンカウンタ、２はＴ型フリツプフロツプ、３お
よび３０はデータロード回路、４，４１および４
２はデータレジスタ、５はＭビツトプリスケーラ
、５１はプログラマブルのＭビツトダウンカウン
タ、５２はデータレジスタを示す。
FIG. 1 is a block diagram showing the configuration of an embodiment of this invention. FIG. 2 is a block diagram showing the configuration of another embodiment of this invention. FIG. 3 shows the M-bit prescaler 5 shown in FIGS. 1 and 2.
This is a timing chart showing the operation. Fourth
The figure shows the PWM output H in the embodiment of FIG.
This is a time chart showing the relationship between the width settings of the pulse and L pulse and the settings in the M-bit prescaler 5. Figure 5 shows the conventional PWM
FIG. 2 is a block diagram showing the configuration of an example of a circuit. 6th
The figure is a block diagram showing the configuration of another example of a conventional PWM circuit. Figure 7 shows the PW shown in Figure 6.
This is a time chart showing the operation of the M circuit. FIG. 8 is a time chart showing the operation of the PWM circuit shown in FIG. 6. In the figure, 1 is a programmable N-bit down counter, 2 is a T-type flip-flop, 3 and 30 are data load circuits, 4, 41 and 4
2 is a data register, 5 is an M-bit prescaler, 51 is a programmable M-bit down counter, and 52 is a data register.
補正 平１．１１．６
図面の簡単な説明を次のように補正する。
明細書第１７頁第２０行の「第６図に示す」を
「第５図に示す」に補正する。Amendment 1.11.6 The brief description of the drawing is amended as follows. "As shown in FIG. 6" on page 17, line 20 of the specification is corrected to "as shown in FIG. 5."
Claims (1)
信号を計数しその計数値が所定の値に達すると出
力の状態を反転する第１のサイクルと、当該第１
のサイクルの終了後予め定められた第２の設定値
から基準クロツク信号を計数しその計数値が所定
の値に達すると出力の状態を再び反転する第２の
サイクルとを交互に繰返し、前記第１および第２
の設定値のいずれか一方あるいは両方を変えるこ
とにより出力パルスのデユーテイ比を変化させる
ようなパルス幅変調回路において、 その分周比が任意に設定可能でかつ当該分周比
で前記基準クロツク信号を分周するための可変分
周手段を備え、当該可変分周手段の出力を計数す
るようにしたことを特徴とする、パルス幅変調回
路。[Claims for Utility Model Registration] A first cycle in which a reference clock signal is counted from a predetermined first set value and the state of the output is inverted when the counted value reaches a predetermined value;
After the completion of the cycle, the reference clock signal is counted from a predetermined second set value, and when the counted value reaches a predetermined value, the output state is inverted again, and the second cycle is repeated alternately. 1st and 2nd
In a pulse width modulation circuit that changes the duty ratio of the output pulse by changing one or both of the setting values, the frequency division ratio can be arbitrarily set, and the reference clock signal is controlled at the frequency division ratio. 1. A pulse width modulation circuit comprising variable frequency dividing means for frequency division, and counting the output of the variable frequency dividing means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11829989U JPH076498Y2 (en) | 1989-10-11 | 1989-10-11 | Ion exchange resin measuring device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11829989U JPH076498Y2 (en) | 1989-10-11 | 1989-10-11 | Ion exchange resin measuring device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0357632U true JPH0357632U (en) | 1991-06-04 |
| JPH076498Y2 JPH076498Y2 (en) | 1995-02-15 |
Family
ID=31666475
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11829989U Expired - Lifetime JPH076498Y2 (en) | 1989-10-11 | 1989-10-11 | Ion exchange resin measuring device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH076498Y2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3627841B2 (en) * | 1998-05-29 | 2005-03-09 | アマノ株式会社 | Sensor device for saturated saline generator |
-
1989
- 1989-10-11 JP JP11829989U patent/JPH076498Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH076498Y2 (en) | 1995-02-15 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |