JPH0322436U

JPH0322436U -

Info

Publication number: JPH0322436U
Application number: JP8377189U
Authority: JP
Priority date: 1989-07-17
Filing date: 1989-07-17
Publication date: 1991-03-07

Description

[Brief explanation of drawings]

第１図は、本考案の一実施例を示す回路図、第
２図はエツジ比較器を用いたＰＬＬ回路を示す回
路図、第３図イ及びロは第２図の説明に供する為
の波形図、第４図イ及びロは第２図の説明に供す
る為の波形図、及び第５図イ乃至ヘは第１図の説
明に供する為の波形図である。２……ＶＣＯ、３……１／ｎ分周器、４……エ
ツジ比較器、６……平滑回路、８……クロツク信
号源、１３……基準電源、１４……スイツチ、１
５……オアゲート、１６……検出手段。 Fig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2 is a circuit diagram showing a PLL circuit using an edge comparator, and Fig. 3 A and B are waveforms for explaining Fig. 2. 4A and 4B are waveform diagrams for explaining FIG. 2, and FIGS. 5A to 5F are waveform diagrams for explaining FIG. 1. 2...VCO, 3...1/n frequency divider, 4...Edge comparator, 6...Smoothing circuit, 8...Clock signal source, 13...Reference power supply, 14...Switch, 1
5...OR gate, 16...detection means.

Claims

[Scope of Claim for Utility Model Registration] (1) A VCO whose oscillation frequency changes and whose gain changes according to a control voltage from a control terminal, and a detection means for detecting that the oscillation of the VCO has stopped. , a reference power supply that generates a voltage at a level sufficient to start the oscillation of the VCO, and a switch that applies a reference voltage from the reference power supply to a control terminal of the VCO in accordance with the detection output of the detection means. An oscillation starting circuit comprising: (2) The detection means includes a frequency divider that divides the frequency of the oscillation output signal of the VCO, and a first AND gate that takes a logical product of the clock signal from the clock signal source and the frequency-divided output signal of the frequency divider. an edge extraction circuit that extracts an edge of the clock signal; a flip-flop that inverts according to the output signals of the first AND gate and the edge extraction circuit; and an inverted signal of the clock signal and an output signal of the flip-flop. 2. The oscillation starting circuit according to claim 1, further comprising: a second AND gate that takes a logical product. (3) an edge comparator that performs an edge comparison between the oscillation output signal of the VCO and the input signal; a smoothing circuit that smoothes the comparison output of the edge comparator; and an output signal of the smoothing circuit and a reference voltage from the switch. an OR gate that takes the logical sum of
2. The oscillation starting circuit according to claim 1, wherein the voltage is applied to the control terminal of the oscillation starting circuit.