JPS5830237A - Step-out detecting system of feedback type phase controlling circuit - Google Patents

Abstract

PURPOSE:To detect step-out, and to generate an alarm information immediately and exactly, by detecting the case when a reference pulse and a feedback pulse do not appear alternately and regularly in an input of a phase comparing circuit. CONSTITUTION:To an AND circuit 10, a reference pulse of a phase comparator 1 and an output of Q are inputted through a delaying circuit 12. To a circuit 11, a feedback pulse and an output of -Q are inputted through a delaying circuit 13. To an OR circuit 9, outputs of the circuits 10, 11 are inputted. In case when a feedback type phase controlling circuit (hereinafter called a PLL circuit) is normal, a time difference between the reference pulse and the feedback pulse is controlled so as to become almost constant, and the circuits 10, 11 generate no output. If an abnormal state occurs, an output is generated in the circuit 10 or 11, and it is sent out as an alarm signal through the circuit 9. Accordingly, it is possible to detect such an abnormal state as step-out and to generate an alarm exactly and immediately without being influenced by a variation of an electric power supply.

Description

DETAILED DESCRIPTION OF THE INVENTION This feedback type phase control circuit inputs a real line reference pulse and outputs a pulse phase-synchronized with it, which instantly and reliably detects out-of-synchronization and immediately performs Kll@. This invention relates to an out-of-synchronization detection method for a feedback phase control circuit.

With recent technology, in order to improve reliability, requests for detecting abnormalities in each block and issuing immediate cost reports are increasing.

In many cases, when the feedback type phase control circuit (hereinafter referred to as PLL1 circuit) is out of synchronization, the device 7ab that detects this and issues an alarm cannot be pressed, but there are examples as shown below.

Figure 1 is a schematic diagram of a conventional PLL circuit, its younger brother (b).
(6) shows the reference pulse waveform, (to) shows the output waveform of the phase comparator l, and FIG. 3 shows the amplification 9 of FIG.
3 is a diagram showing the relationship between the upper limit voltage Vlll and the lower limit voltage VL for determining whether the output voltage (We) is normal or abnormal.

In the figure, 1 is a phase comparator circuit (7 lips), 2 is a reduction filter, 3 is an amplifier, 4 is a voltage controlled y# oscillation 41 (
(hereinafter referred to as vCO), the device is a 1/1 frequency divider, the art is a differentiation circuit, 7.8 is a voltage comparator, 9 is an OR circuit, and VC is an amplification circuit.
3 shows the output voltage, VHd upper limit voltage, and vL line lower limit voltage. In operation, a reference pulse as shown in s2 ([)K and a feedback pulse as shown in Fig. 2(C) K are sent to the phase comparator l.
Input it to the giant T and RESET terminal. The output shown in the second figure) obtained by this input is inputted to the VCO4 as an average voltage via the waveform generator 2 and the amplifier 3.
controls the frequency of Also, the frequency of VCO4 is 1/r
The IL frequency divider 5 is set to 1/Atsu as shown in Fig. 2 03),
This waveform is differentiated by a differentiating circuit 6 at the falling point and shown in Fig. 2 (C
) is outputted and returned to the phase comparator 1 as a feedback pulse. When the phase of the reference pulse and the feedback pulse is shifted, the width of the high level of the output of the phase comparator 1 shown in (■) changes, so the source of the output voltage Vc of the amplifier 3 changes, and the oscillation frequency of the VCO 4 is changed to return to the next one. I'm dying to return. The normal width of the output voltage Vc of the amplifier 43, that is, the dynamic range, is such that the phase difference between the output pulse of the differentiating circuit 6 shown in C) and the reference pulse shown in ) is 1/m for one pulse of the frequency divider 5. Maximum when there is only width ′&
If there are nine overlaps, it becomes O. However, in this circuit, if the full dynamic range is considered normal, it is impossible to judge whether it is normal or abnormal, so as shown in FIG.
Add it to 8. This 'voltage and the output voltage FE of the amplification h3
Vc and if it exceeds this voltage, it is considered abnormal and the outputs of the voltage amplifiers 7 and 8 are set to high level and the OR circuit 9
An alert is issued via. However, this method has the drawback of not narrowing the dynamic range as explained above, and since voltage comparators 7 and 8 are analog voltage comparators, the criteria for determining abnormality due to voltage fluctuations It has the disadvantage of being unsteady.

The object of the present invention is to provide a PLL circuit that can immediately and reliably issue out-of-synchronization alarm information by adding a simple logic element to eliminate the above-mentioned drawback. In order to achieve the above object, the invention uses a reference Noculus,
PLL with a phase comparator that compares the phase of feedback pulses
In (b), by detecting a combination in which the reference pulse and the # return pulse do not appear alternately and regularly in the input of the phase comparator circuit, it is possible to detect p-synchronization and eliminate the problem.
? be a sign.

An example of a rush current according to the present invention will be explained below according to the figures. 〇 Figure 4 shows the embodiment of the present invention and shows the output circuit of the abnormality detection alarm output circuit, and Figure 5 shows the reference current pulse and feedback pulse in the case of Figure 4. 7tz of operation due to normal abnormality (A)-
1 indicates the reference pulse s (A) during normal operation, -2 indicates the feedback pulse, and -3 indicates the output of Q of the phase comparator 1.
The reference pulse at the time of abnormality, ω)-2 extensional pulse is shown, and (
C) (2) shows the output of the phase comparator If)Q and the output of the AND circuit 10 in the case of (8), @-1 is the reference pulse at the time of abnormality, @-2 is the feedback nox, and vI (to) is (
The output of q of phase comparator 1 and AND@@1 in the case of
FIG. 6 is a diagram showing the relationship between the pulse width of the reference pulse or the feedback pulse and the rising edge of the outputs of Q and Q of the phase comparator 1.

Components in the figure that have the same functions as those in FIG. 1 are indicated by the same symbols.

10.11 shows an AND circuit, and 12.13 shows a delay circuit.

A circuit that inputs the reference pulse of the phase comparator l and the output of Q shown in the first factor of FIG. A circuit is set up to input the outputs of the AND circuits 10 and 11 to the AND circuit 11 via the OR circuit 9.If the PLL circuit is normal, the reference pulse and feedback pulse are input as shown in Figure 5. The time difference is controlled to be approximately constant, and the output of the phase comparator 1f)Q does not appear in the shand circuit 10 as shown in the figure. Since the output of X4 is also opposite to Q, the AND circuit 11 has the correct output l.
/'0, that is, in the normal state, there is some kind of abnormality as shown in the standard no. When the pulse becomes positive at the table shown in (C) and (2), the output of Q of phase comparator 1 becomes E, as shown in (C)K. comes and circuit 1
A pulse is generated at the output of 0 as shown in (c), and an abnormal state can be detected and sent as an alarm signal via the OR circuit 9. In other words, if we look at the point E, we can see that the relationship between the reference point and the feedback pulse is not A, W, but A, A. This situation is the same even when the feedback loop is broken. In this case, the feedback pulse is not total heat, so it is a.

It emits a series of A and A and an alarm signal. The same phenomenon occurs when the loop circuit is disconnected and the PLL circuit is not turned off and the frequency of the feedback pulse is lower than normal. Also, as shown in (g), if the loop circuit is not ranged and the frequency of the feedback pulse is higher than normal, the phase comparator 4 of phase comparator 1 shown in (g)
Since the next feedback pulse comes while the output of 4 is at a high level at the point shown in G of the output of , a pulse is generated at the output of the AND circuit 11 as shown at the beginning. It is sent as an alarm signal via the In other words, the relationship between the reference pulse I and the feedback pulse port is not 0 at point G, but is 1 port.In other words, in an abnormal situation, there always occurs a point where the relationship between the reference pulse I and the feedback pulse port does not alternate. Therefore, the present invention focuses on this point. Since the signal does not go through a reduction filter, there is no delay, and the logic element detects the signal, so it is not affected by power fluctuations. If we look at the details, as shown in Figure 6, the relationship between the reference pulse and the Q output of the phase comparator 1 is that the Q output may be 1 within the pulse width of the reference pulse [see Figure 4]. In the circuit, a delay circuit 12 is provided to
By delaying by I, false alarms during normal operation are eliminated. Since this problem occurs due to the relationship between the Q of the feedback pulse and the phase comparison 'a1, a similar delay circuit 13 is provided.

As explained in detail above, according to the present invention, VC.

This has the effect of being able to reliably and immediately detect an out-of-synchronization abnormality and issue an alarm without narrowing the dynamo range of the input voltage and without being affected by power fluctuations.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional PLL circuit, FIG. 2 is a time chart for the case of FIG. 1, and FIG. 3 is a dynamic range and upper limit of the output voltage Vc of the amplifier 3 for the case of FIG.
1I14 is a block diagram of an abnormality detection alarm output circuit according to an embodiment of the present invention, FIG. 5 is a flowchart of the operation in the case of FIG. 4, and FIG. 6 is a standard 2 is a diagram showing the relationship between the pulse width of a pulse or a feedback pulse and the rise of the output of q and cli of the phase comparator 1. FIG.

Claims (1)

[Claims] Phase ratio II that compares the phase of the reference pulse and the feedback pulse
In the feedback type phase control circuit having RIIt, a means for detecting an abnormality in the order regularity between the reference pulse and the feedback pulse is provided, and an out-of-synchronization is detected by the output of the scissor detection means. Out-of-sync detection method for phase control circuit