JPH0322438A - Manufacture of bipolar semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To eliminate the need for the consideration of the allowance of mask alignment on a process, and to obtain an integrated circuit device having excellent high- speed workability by low power consumption by conducting a photoetching process once when an element isolation region is formed and shaping all of the inert base region, active base region and emitter region through self-alignment. CONSTITUTION:An N<+> type buried diffusion layer 102 and an N<-> type epitaxial Iayer 103 are shaped to a P<-> type semiconductor substrate 101, and a pad oxide film 104 is formed onto the surface of the layer 103 and a first silicon nitride film 105, a first polycrystalline silicon film 106 and a silicon nitride film 107 onto the pad oxide film 104. A resist pattern is shaped onto the silicon nitride film 107 by using a photolithographic technique, and trenches 108 are formed at positions, where element isolation oxide films must be shaped, through specified etching while using the resist pattern as a mask. A specified process only by self-alignment is executed without mask alignment with an island region 103a, and an inert base region 114 is formed into the island region 103a, an active base region 117 into the region 114 and an emitter region 119 into the region 117 respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a bipolar semiconductor integrated circuit device that is highly integrated and capable of high-speed operation.

(Prior Art) In fields where semiconductor integrated circuit devices are particularly required to operate at high speed, bibolar semiconductor integrated circuit devices based on ECL/CML are generally used. ECL/CM
In the L-system circuit device, power consumption. When the logic amplitude is constant, the operating speed is determined by the parasitic capacitance of the elements and wiring that make up the circuit, the base resistance of the transistor, and the gain-bandwidth product. Among these, to reduce parasitic capacitance, it is necessary to reduce the junction capacitance between the base and collector of transistors, which has a particularly large contribution to operating speed. It is effective to reduce the area of the extraction base outside the element region. Furthermore, a method is generally employed in which a polycrystalline silicon resistor and metal wiring are formed on a thick isolation oxide film to reduce their parasitic capacitance.

On the other hand, to reduce the base resistance, it is necessary to lower the resistance of the inactive base layer and place it as close as possible to the emitter ξ vines, and to make the engineered ξ vines thinner to reduce the resistance of the active base layer directly under the emitter. It is.

Furthermore, in order to improve the gain bandwidth product, it is effective to make the emitter and base junctions shallower and to make the epitaxial layer in the collector nodal region thinner.

As a conventional technique aimed at realizing these matters, a method for manufacturing a bipolar transistor using a conventional double polysilicon structure will be described with reference to FIG.

First, as shown in FIG. 2(A), a P-type semiconductor substrate 2 is prepared.
After forming an N-type buried diffusion layer 202 on the semiconductor substrate 01 and forming an N-type epitaxial layer 203 on the semiconductor substrate using an epitaxial technique, a pad oxide film 204 is formed, and a nitride film 205 is formed on the top surface thereof. .

Next, a resist pattern (not shown) is formed on the nitride film 205 using a known photolithography technique, and the nitride film 205 and the pad oxide film 204 are etched using the resist pattern as a mask. Furthermore, using the remaining pad oxide film 204 and nitride film 205 as a mask, an N-type epitaxial layer 2 is formed.
03 is selectively etched to form a groove 206 at a position where an element isolation oxide film is to be formed later, as shown in FIG. 2(B). By forming this groove, the N-type epitaxial layer 2
03, an illustrated first island region 203a and an unillustrated second island region are formed.

Next, as shown in FIG. 2(c), thermal oxidation is performed to form the groove 20.
6, a thick element isolation oxide film 20 made of a silicon oxide film layer;
form 7.

Next, after removing the nitride film 205, which is an oxidation-resistant mask, a resist mask (not shown) is formed and phosphorus is ion-implanted only into the second island region (not shown). By performing heat treatment in a neutral atmosphere, the second island region is made of N9 for collector resistance reduction.
Type area.

Next, after removing the pad oxide film 204, the entire surface is
A first polycrystalline silicon film 20B is formed as shown in FIG.

Further thermal oxidation is performed to form a polycrystalline silicon oxide film 209 on the surface of the first polycrystalline silicon film 208. Subsequently, boron ions are implanted into the first polycrystalline silicon film 208. Thereafter, a resist pattern 210 is formed on the polycrystalline silicon oxide film 209 using photolithography technology.

Then, the polycrystalline silicon oxide film 209 is etched by anisotropic etching using the resist pattern 210 as a mask, and then the first polycrystalline silicon film 208 is etched, thereby removing the polycrystalline silicon oxide film 209 as shown in FIG. As shown in the figure, an opening 211 for forming an active base and an ivy is formed on the first island region 203a.Then, the resist pattern 210 is removed as shown in the figure.

Next, the first island region 203a exposed by the opening formation
After oxidizing the surface thinly, a CVD oxide film 212 is formed on the entire surface as shown in FIG. 2(F). At this time, a highly concentrated inactive base region 213 is formed by diffusion of boron from the first polycrystalline silicon film 208 at the side end portion of the first island region 203a in contact with the first polycrystalline silicon film 20B. Ru.

Next, by etching the CVD oxide film 212 by anisotropic etching, as shown in FIG.
CV.
Sidewalls 212a of the D oxide film 212 are formed.

Thereafter, boron ions are implanted into the first island region 203a through the opening 211 narrowed by the sidewall 212a, and heat treatment is performed in a non-oxidizing atmosphere to form the active base region 214 as shown in the figure. It is formed within the first island region 203a.

Next, after forming a second polycrystalline silicon film 215 on the entire surface, arsenic ions are implanted into this second polycrystalline silicon film 215, and then the second polycrystalline silicon film 215 is patterned by known photolithography and etching. By performing this, the second polycrystalline silicon film 215 is formed as shown in FIG.
As shown in Fig. H), a vine electrode is left in the opening 211 and its surrounding area, and a collector electrode is left on an N-type region for reducing collector resistance (not shown). After that, the surface of the remaining second polycrystalline silicon film 215 is thinly oxidized, and then heat-treated in a non-oxidizing atmosphere to diffuse arsenic from the second polycrystalline silicon film 215 into the active base region 214 and activate the active base region 214. An emitter region 216 is formed within base region 214 . With the above steps, the element is completed.

(Problem to be Solved by the Invention) However, in the conventional manufacturing method as described above, the first island region 2 inside the element isolation region which is preformed
03a, the polycrystalline silicon oxide film 209 and the first
Since the polycrystalline silicon film 20B must be selectively etched, it is necessary to ensure a margin for mask alignment in the first island region 203a, which increases the size of the first island region 203a, which contributes to the reduction of the area occupied by the transistor. Give a limit, especially the base-collector junction capacitance C? . There was a point at which it was difficult to reduce.

This invention solves the problem that there is a limit to the reduction of the area occupied by transistors due to the securing of mask alignment margins as described above, and manufactures a bibolar type semiconductor integrated circuit device that can further reduce the area occupied by transistors and achieve higher performance. The purpose is to provide a method.

(Means for Solving the Problems) In this invention, when forming the element portion II eI 31i, 1
After performing the photo-etching process, an inert base area is formed. The active base region and emitter region can all be formed in self-alignment.

Specifically, a first oxidation-resistant film is formed on the surface of a semiconductor substrate. After sequentially stacking the first polycrystalline semiconductor layer and the second oxidation-resistant film, this three-layer film is patterned to obtain a predetermined fIJi.
A groove having an undercut is formed under the first oxidation-resistant film on a surface portion of the semiconductor substrate that is not covered with the remaining three-layer film;
The polycrystalline semiconductor layer is side-etched, and the side surface of the first polycrystalline semiconductor layer is retreated. Thereafter, the semiconductor substrate is selectively oxidized using the remaining oxidation-resistant film as a mask to form an elemental IEil# film in the trench, and at the same time, the first polycrystalline semiconductor layer is also oxidized from the side surface. By converting the first polycrystalline semiconductor layer into a film, the side surfaces of the first polycrystalline semiconductor layer are set back. Thereafter, the second oxidation-resistant film and the oxide film on the side surfaces of the first polycrystalline semiconductor layer are removed, and the first oxidation-resistant film is further removed from the portions not covered with the first polycrystalline semiconductor layer. After removing the film, a part of the island region is removed using the first polycrystalline semiconductor layer and the first oxidation-resistant film on the island region portion of the semiconductor substrate surrounded by the element isolation oxide film as a mask. The element isolation oxide film is etched until a portion thereof is exposed. Thereafter, by forming a second polycrystalline semiconductor layer on the entire surface, forming a planarization film, and etching back, a second polycrystalline semiconductor layer is formed so as to be in contact with and extend from the exposed island region. At the same time, the first polycrystalline semiconductor layer on the island region is removed. Thereafter, by impurity diffusion from the second polycrystalline semiconductor layer, an inactive base region of a second conductivity type is formed in a part of the island region of the first conductivity type, and the surface of the second polycrystalline semiconductor layer is A first insulating film is formed thereon. After that, the first oxidation-resistant film on the island region is removed to form an opening, and then the side surface of the second polycrystalline semiconductor layer exposed in the opening portion and the first oxidation-resistant film thereon are removed. l1 A sidewall of a second insulating film is formed on the side wall of the insulating film, and a second conductivity type impurity is introduced into the island region through the opening narrowed by the sidewall and extends into the inactive base region. activity. Form the base area.

Thereafter, a third polycrystalline semiconductor layer doped with a first conductivity type impurity is formed in the narrowed opening portion, and the impurity is diffused from the third polycrystalline semiconductor layer into the active base region. Forming a conductive type emitter region.

(Function) In the above invention, a photolithography process is required when first patterning the three-layer film formed on the surface of the semiconductor substrate, but thereafter the process is carried out on the Selfa line. The inactive base region, active base region, and emitter region are all formed. Therefore, there is no need to take any allowance for mask alignment into consideration in the process.

In fact, as shown in the examples described later, the second
A photolithography process is required to remove unnecessary portions of the second polycrystalline semiconductor layer or to form a third polycrystalline semiconductor layer in the opening 12, but these photolithography processes It does not affect the area of the region and its existence can be ignored. In addition, the inert base area is independent of these photoetching processes. The plant ivy area can be formed with self-alignment.

(Embodiment) An embodiment of the present invention will be described below with reference to FIGS. 1(A) to (K).

First, as shown in FIG. 1(A), a P-type semiconductor substrate 1 is prepared.
After forming an N4 type buried diffusion layer 102 on the semiconductor substrate 01, an N1 type epitaxial layer 103 is formed on the semiconductor substrate by an epitaxial technique, and thermal oxidation is performed on the surface of this N1 type epitaxial layer 103 to form a 200 to 500 layer thickness. A pad oxide film 104 is formed. And on top of that, about 20
A first silicon nitride film 105 with a thickness of 0.000 μm, a first polycrystalline silicon film 106 with a thickness of approximately 3000 μm, and a second silicon nitride film 107 with a thickness of approximately 2000 μm are successively formed.

Next, a resist pattern (not shown) is formed on the second silicon nitride film 107 using a known photolithography technique, and using this as a mask, the second silicon nitride film 107. First polycrystalline silicon film 106, first silicon nitride film 105
After successively etching the remaining second and first silicon nitride films 107, 105 and the pad oxide film 104, the N-type epitaxial layer 103 is selectively etched, as shown in FIG. ), grooves 108 are formed at the positions where the element isolation oxide film is to be formed later.
form. At this time, the groove 108 is partially covered by the pad oxide film 10.
At the same time, the first polycrystalline silicon film 106 is also side-etched, causing the side surface to recede. That is, the upper end of the side surface of the groove 108 and the side surface of the first polycrystalline silicon film 106 are at the same position. Moreover, by forming this groove, a first island region 103a shown in the figure and a second island region not shown are formed in the N1 type epitaxial layer 103.

After that, the second. Using the first silicon nitride films 107 and 105 as a mask, such a semiconductor substrate is thermally oxidized to form grooves 108.
As shown in FIG. 1(c), a thick #oxide film 110 consisting of a silicon oxide film layer is formed on a portion thereof. At this time, the first polycrystalline silicon film 10
6 is also oxidized from the side surface to form a polycrystalline silicon oxide film 109, and the side surface of the first polycrystalline silicon film 106 recedes.

Next, as shown in FIG. 1(D), the second silicon nitride film 107 is removed by immersing it in a solution that selectively dissolves the nitride film, such as phosphoric acid, and then a hydrofluoric acid solution is used to remove the second silicon nitride film 107. Then, polycrystalline silicon oxide film 109 is removed.

Next, although not shown, the first polycrystalline silicon film 106 and the first silicon nitride film 105 on the second island region are removed by dry etching using photolithography, and then phosphorus is etched using a resist as a mask. 10lbcm
-" ions are implanted into the second island region. After that, the resist is removed and heat treatment is performed to transform the second island region into a collector resistance reducing diffusion 6Jf Mi that reaches the N-type buried diffusion layer 102. do.

Next, as shown in FIG. 1E, anisotropic etching is performed using the first polycrystalline silicon film 106 on the first island region 15 103a as a mask to remove the first polycrystalline silicon film 106. The first silicon nitride film 1 in the area not covered by
Remove 05. Subsequently, the oxide film is anisotropically etched to expose the surface of the side end portion of the first island region 103a as shown in the figure.

At this time, the amount of surface exposure of the first island region 103a is determined by the amount of etching of the oxide film. This amount of exposure becomes the size of the inert base that will be formed later.

Next, as shown in Figure 1 (F), 3000 to 500
A second polycrystalline silicon film 111 having a thickness of 0.00 mm is formed. Next, the first island region 1 is formed using photolithography technology.
A resist pattern 112 for planarization is formed so as to surround the convex portion on 03a (consisting of a laminated film of a pad oxide film 104, a first silicon nitride film 105, a first polycrystalline silicon film 111,106, and a second polycrystalline silicon film 111). Form. Subsequently, a resist is applied again and the resist surface is flattened, and then the resist and the second and first polycrystalline silicon films 111 and 106 are etched under conditions such that the etching rates of the resist and the polycrystalline silicon are equal. 1 silicon nitride film 1
Etch until the surface of 05 is exposed. After that, the remaining resist is removed. Through this process, Figure 1 (G)
As shown in , the first polycrystalline silicon film 106 is completely removed, and the second polycrystalline silicon film 111 is in contact with the side end surface of the first island region 103a, and the first silicon nitride film 1
05 remains extending from the first island region 103a.

Next, after thinly oxidizing the surface of the second polycrystalline silicon film 111, boron ions of about 1 to 5 x 10 cm- are implanted over the entire surface, and then a base extraction electrode region is defined using photolithography technology. Therefore, unnecessary second polycrystalline silicon film 111 is removed.

Next, by performing heat treatment at 900°C to 950°C, the second polycrystalline silicon film 1 is heated as shown in FIG.
An inactive base region 114 is formed within the side edge of the first island region 103a by diffusion of boron from 11, and at the same time the surface of the second polycrystalline silicon film 111 is oxidized to
A polycrystalline silicon oxide film 113 with a thickness of 0A is formed.

Next, the first silicon nitride film 105 is removed by immersing it in a solution that selectively dissolves the nitride film, such as phosphoric acid, and an opening 115 is formed. Thereafter, as shown in FIG. 1(I), a CVD oxide film 116 (instead of the CVD oxide film, a silicon nitride film or an oxide film may be formed by sputtering) is formed on the entire surface.

Next, by performing anisotropic etching to etch back the CVD oxide film 116, as shown in FIG. Residual CVD on the side of the membrane 113
Sidewalls 116a of the oxide film 116 are formed. Then, through the opening 115 narrowed by the sidewall 116a, boron is added in an amount of 1 to 5×10”c.
After implanting ions into the first island region 103a to a depth of approximately 900° C., an active base region 117 is formed within the first island region 103a.

17 18 Next, anisotropic etching is performed to remove the exposed pad oxide film 10.
After removing 4, the third polycrystalline silicon llI11B
is formed on the entire surface. After the surface of this third polycrystalline silicon film 118 is thinly oxidized (not shown), this third polycrystalline silicon film 118 is
Arsenic ions of about 10"411-" are implanted into the polycrystalline silicon film 11B. Thereafter, the third polycrystalline silicon film 118 is etched using photolithography technology, and the second polycrystalline silicon film 118 is etched.
As shown in Figure (K), after leaving the third polycrystalline silicon film 118 as an emitter electrode in the opening 115 and its surrounding area and as a collector electrode on the collector resistance reduction diffusion region (not shown), a An emitter region 119 is formed in the active base region 117 by diffusing arsenic from the 3-polycrystalline silicon film 11B.

With this, Motoko has completed his premonition.

(Effects of the Invention) As described above in detail, according to the manufacturing method of the present invention, after one photolithography process is performed when forming the element III SM region, the inactive base region is formed. Active base region. Since the entire emitter region can be formed into a shape 19 by self-alignment, there is no need to consider mask alignment margins in the process. Therefore, the island region can be narrowed, and in the bipolar transistor formed in this region, the base area can be reduced to about 40% of the conventional one with the same design standard, and the junction capacitance CTC of the pace collector can be reduced. Since the power consumption is significantly reduced, a bipolar semiconductor integrated circuit device with low power consumption and excellent high-speed operation can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a process sectional view showing an embodiment of the method for manufacturing a bibolar type semiconductor integrated circuit device of the present invention, and FIG. 2 is a process sectional view showing a conventional manufacturing method. 101...P type semiconductor substrate, 103...N type epitaxial layer, 103a...first island region, 105
. . . first silicon nitride film, 106 . . . first polycrystalline silicon film, 107 . . . second silicon nitride film, 108.
...Groove, 109...Polycrystalline silicon oxide film, 110.
... Element isolation oxide film, 111... Second polycrystalline silicon film, 112... Resist pattern, 113... Polycrystalline silicon 20 silicon oxide film, 114... Inactive base region, 115...
...Opening, 116...CVD oxide film, 116a...
- Sidewall, 117...Active base region, 11
B...Third polycrystalline silicon film, 119...Emitter region. 21 1030 1050 Process sectional view of the present invention Fig. 1 Process sectional view of the conventional method Fig. 2

Claims (1)

[Claims] (a) After sequentially laminating a first oxidation-resistant film, a first polycrystalline semiconductor layer, and a second oxidation-resistant film on the surface of a semiconductor substrate, patterning the three-layer film (b) forming a groove having an undercut under the first oxidation-resistant film in a surface portion of the semiconductor substrate not covered with the remaining three-layer film; and (c) then, selectively etching the semiconductor substrate using the remaining oxidation-resistant film as a mask. oxidation to form an element isolation oxide film in the trench, and at the same time, the first polycrystalline semiconductor layer is also oxidized from the side surfaces and converted into an oxide film, thereby causing the side surfaces of the first polycrystalline semiconductor layer to retreat. (d) After that, the second oxidation-resistant film and the oxide film on the side surfaces of the first polycrystalline semiconductor layer are removed, and the portions not covered with the first polycrystalline semiconductor layer are removed. (e) removing the first oxidation-resistant film and the first polycrystalline semiconductor layer on the island region of the semiconductor substrate surrounded by the element isolation oxide film; etching the element isolation oxide film using the oxidizing film as a mask until a part of the island region is exposed; forming a second polycrystalline semiconductor layer in contact with and extending from the exposed island region by backing, and removing the first polycrystalline semiconductor layer on the island region; (g) Thereafter, an inactive base region of a second conductivity type is formed in a part of the island region of the first conductivity type by impurity diffusion from the second polycrystalline semiconductor layer, and an inactive base region of a second conductivity type is formed in a part of the island region of the first conductivity type. forming a first insulating film on the surface of the crystalline semiconductor layer; (h) after that, forming an opening by removing the first oxidation-resistant film on the island region; forming a sidewall of a second insulating film on the exposed side surface of the second polycrystalline semiconductor layer and the side surface of the first insulating film thereon; (i) the opening narrowed by the sidewall; (j) introducing an impurity of a second conductivity type into the island region through the opening to form an active base region extending into the inactive base region; forming an impurity-doped third polycrystalline semiconductor layer, and forming an emitter region of the first conductivity type in the active base region by impurity diffusion from the third polycrystalline semiconductor layer. A method for manufacturing a bipolar semiconductor integrated circuit device.