JPH0322439A - Method for manufacturing semiconductor integrated circuit device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a semiconductor integrated circuit device that is highly integrated and capable of high-speed operation.

(Prior Art) In fields where semiconductor integrated circuit devices are particularly required to operate at high speed, ECL/CML-based high-volume semiconductor integrated circuit devices are generally used. ECL/CM
In an L-system circuit device, when power consumption and logic amplitude are constant, the operating speed is determined by the parasitic capacitance of the elements and wiring that make up the circuit device, the base resistance of the transistor, and the gain-bandwidth product. Among these, to reduce parasitic capacitance, it is necessary to reduce the junction capacitance between the base and collector of transistors, which has a particularly large contribution to operating speed. It is effective to reduce the base area by drawing it outside the element area. Furthermore, a method is generally employed in which a polycrystalline silicon resistor and metal wiring are formed on a thick isolation oxide film to reduce their parasitic capacitance.

On the other hand, to reduce the base resistance, it is necessary to lower the resistance of the inactive heath layer and place it as close to the vine as possible, and to make the emitter thinner to reduce the resistance of the active base layer directly below the emitter. .

Furthermore, in order to improve the gain bandwidth product, it is effective to make the emitter and base junctions shallower and to make the epitaxial layer in the collector region thinner.

As a conventional technique aimed at realizing these matters, a method of manufacturing a bipolar transistor using a double polysilicon structure previously proposed by the present inventor will be described with reference to FIG.

First, as shown in FIG. 2(A), a P-type semiconductor substrate 2 is prepared.
After forming an N-type buried diffusion layer 202 on 01, an N-type epitaxial layer 203 is formed on the semiconductor substrate by the epitaxial technique, and thermal oxidation is performed on the surface of this N1-type epitaxial N203. A thick pad oxide film 204 is formed. And on top of that, about 2
A first silicon nitride film 205 with a thickness of 0.000 μm, a first polycrystalline silicon film 206 with a thickness of approximately 3000 μm, and a second silicon nitride film 207 with a thickness of approximately 2000 μm are successively formed.

Next, a resist pattern (not shown) is formed on the second silicon nitride film 207 using a known photolithography technique, and using this as a mask, the second silicon nitride film 207. After successively etching the first polycrystalline silicon film 206, first silicon nitride film 205, and pad oxide film 204,
Second. Using the first silicon nitride films 207 and 205 and the pad oxide film 204 as a mask, the N-type epitaxial layer 20 is formed.
3 is selectively etched, as shown in FIG. 2(B).
A trench 208 is formed at a position where an element isolation oxide film is to be formed later. At this time, the groove 208 is partially under-etched under the pad oxide film 204, and at the same time, the first polycrystalline silicon film 206 is also side-etched. That is, groove 2
The upper end of the side surface of 08 and the side surface of the first polycrystalline silicon film 206 are at the same position. Moreover, due to this groove shape, the N-type epitaxial layer 203 has the first island region 2 shown in the figure.
03a and a second island region (not shown) are formed.

After that, such a semiconductor substrate is thermally oxidized to form a thick element isolation oxide film 21 made of a silicon oxide film layer in the groove 208 portion.
0 is shaped as shown in FIG. 2(c). At this time, the first polycrystalline silicon film 206 is also oxidized and a polycrystalline silicon oxide film 209 is formed.

Next, as shown in FIG. 2(D), the second silicon nitride film 207 is removed by immersing it in a solution that selectively dissolves the nitride film, such as phosphoric acid, and then the second silicon nitride film 207 is removed using a hydrofluoric acid solution. Remove polycrystalline silicon oxide Ii4209.

Next, although not shown, after removing the first polycrystalline silicon film 206 and first silicon nitride film 205 on the second island region by dry etching using photolithography technology, phosphorus is subsequently etched using a resist as a mask. IQ"cm-
After that, the resist is removed and heat treatment is performed to make the second island Sa region a collector resistance reduction diffusion region that reaches the N+ type buried diffusion layer 202.

Next, as shown in FIG. 2(E), the first island region 203
Using the first polycrystalline silicon film 206 on a as a mask, anisotropic etching is performed to remove the first polycrystalline silicon film 206.
The first silicon nitride film 205 in the area not covered by the first silicon nitride film 205 is removed. Next, anisotropic etching of the oxide film is performed,
As shown in the figure, the surface of the side end portion of the first island region 203a is exposed.

At this time, the amount of surface exposure of the first island region 203a is determined by the amount of etching of the oxide film. This amount of exposure is
This will be the dimension of the inert base that will be formed later.

Next, as shown in Figure 2 (F), 3000 to 50
A second polycrystalline silicon film 211 having a thickness of 0.00 mm is formed. Next, the first island region 2 is formed using photolithography technology.
A resist pattern 218 for flattening is formed so as to surround the convex portion on 03a. Subsequently, after applying resist again and flattening the resist surface, the resist and the second and first polycrystalline silicon films 211 and 206 are etched under conditions such that the etching rate of the resist and the polycrystalline silicon are equal.
is etched until the surface of the first silicon nitride film 205 is exposed. After that, the remaining resist is removed. Through this step, as shown in FIG. 2(G), the first polycrystalline silicon film 206 is completely removed, and the second polycrystalline silicon film 211 is in contact with the side edge surface of the first island region 203a. It remains on the surface except for the first silicon nitride film 205.

Next, after thinly oxidizing the surface of the second polycrystalline silicon film 211, boron ions are implanted into the entire surface at a thickness of about 1 to 5 x 101 scm, and then photolithography is used to define the base extraction electrode area. Therefore, unnecessary second polycrystalline silicon film 241 is removed.

Next, by performing heat treatment at 900°C to 950°C, the second polycrystalline silicon film 2
An inactive base region 213 is formed within the side edge of the first island region 203a by diffusion of boron from 11, and at the same time the surface of the second polycrystalline silicon film 211 is oxidized to
A 0-thick polycrystalline silicon oxide Wi4212 is formed.

Next, the first silicon nitride film 205 is removed by immersing it in a solution that selectively dissolves the nitride film, such as phosphoric acid. After that, as shown in FIG. 2(1), a CVD oxide film 214 (silicon nitride film or
An oxide film may be formed by sputtering.

Next, by performing anisotropic etching and etching back the CVD oxide film 214, as shown in FIG. part and polycrystalline silicon oxide film 212
At the end, the sidewall 21 of the remaining CVD oxide film 214
Form 4a.

Thereafter, 1 to 5 boron is added through the first silicon nitride film removed portion narrowed by the sidewall 214a.
X 10 l″am-” degree, first island H'l420
After ion implantation into the first island region 203a, an active base region 215 is formed in the first island region 203a by performing heat treatment at about 900°C.

Next, anisotropic etching is performed to remove the exposed pad oxide film 20.
4, a third polycrystalline silicon film 216 is formed on the entire surface. Then, this third polycrystalline silicon film 21
After oxidizing the surface of the third polycrystalline silicon film 216 thinly (not shown), arsenic ions of about 1016cII1-2 are introduced into the third polycrystalline silicon film 216. After that, a third polycrystalline silicon film 2 is formed using photolithography technology.
16 to form the first
After leaving the third polycrystalline silicon film 216 on the island region 203a and the surrounding vi region as a zigzag electrode and as a collector electrode on the collector resistance reduction diffusion region (not shown), heat treatment is performed to form the third polycrystalline silicon film 216. By diffusing arsenic from film 216, the active base region 215
An ivy area 217 is formed inside. With this, Motoko has completed his premonition.

According to the above method, the separated region. Since the shapes of the base region and the vine region are all self-aligned,
There is no need for a photolithography process to determine the position of each region, and there is no need to ensure mask alignment margin in the same process.As a result, it is possible to significantly reduce the base area and the area occupied by the transistor, and cTc (
This has a significant effect on speeding up by reducing collector capacitance) and CtS (collector-to-substrate capacitance).

(Problems to be Solved by the Invention) l1 However, in the previously proposed manufacturing method as described above, when removing the polycrystalline silicon oxide film 209 shown in FIG. Since the oxide film 210 is also etched at the same time, there is a problem in that a large depression is formed in the element isolation oxide film 210 as shown in FIG. 2(0). Furthermore, in the above method, when forming the element isolation oxide film 210, a bulge of the oxide film, a so-called bird's head, occurs at the end of the element isolation oxide film, and a severe step is formed by overlapping with the generation of the large depression. There was a point. The occurrence of this large step can cause disconnection in the metal electrode wiring layer or other wiring layers that cross it in multilayer wiring, or even if it does not result in a disconnection, it can cause a decrease in interconnect reliability due to a local decrease in film thickness at the step. This is a problem that reduces performance and imposes design restrictions on transistors realized using the above technology.

This invention solves the above-mentioned problem of large steps occurring in the element isolation oxide film, and achieves high performance. An object of the present invention is to provide a method for manufacturing a semiconductor integrated circuit device that can realize a highly reliable semiconductor integrated circuit device.

(Means for Solving the Problems) In the present invention, before forming the element isolation oxide film, the sidewalls of the trench formed in the semiconductor substrate and the side surfaces of the first polycrystalline semiconductor layer on the semiconductor substrate island region are A third oxidation-resistant film is formed.

(Function) In the present invention, an oxidation step is performed with the third oxidation-resistant film formed to form an element isolation oxide film. At this time, the third oxidation-resistant film is The formation of the oxidizing film prevents the occurrence of bird's heads. Further, since the third oxidation-resistant film is similarly formed on the side surface of the first polycrystalline semiconductor layer, formation of a polycrystalline semiconductor oxide film on this first polycrystalline semiconductor layer portion is prevented, and therefore This eliminates the step of removing the polycrystalline semiconductor oxide film, thereby eliminating the possibility of partially etching the element isolation oxide film at the same time.

(Example) An example of the present invention will be described below with reference to FIG.

First, as shown in FIG. 1(A), a P-type semiconductor substrate 1 is prepared.
After forming an N-type buried diffusion layer 102 on the semiconductor substrate, an N-type epitaxial layer 103 is formed on the semiconductor substrate, and the surface of this N-type epitaxial layer 103 is thermally oxidized to form a first pad oxide film 104 on the semiconductor substrate. The first silicon nitride film 105 is deposited on the first silicon nitride film 105 to a thickness of about 2,000 layers.
After depositing the first polycrystalline silicon film 106 by approximately 3000 people and the second silicon nitride film 107 thereon by approximately 2000 people, an isolation oxide film is formed using photolithography technology and RIB (reactive ion etching) method. The second silicon nitride film 107, first polycrystalline silicon film 106, and first silicon nitride film 105 in the desired area are removed by sequential anisotropic etching, and then the first pad oxide film 104 in the same area is wet etched. and remove it.

Next, as shown in FIG. 1B, the N1 type epitaxial layer 103 is etched from the removed portion using a wet etching method or a CF etching method. Grooves 108 are formed by a plasma etching method using a system gas. At this time, the trench 108 has an undercut portion under the first pad oxide film 104 due to side etching. Further, at this time, the first polycrystalline silicon film 106 is also side-etched in the same manner.

Therefore, the upper end of the side surface of trench 10B and the side surface of first polycrystalline silicon film 106 are approximately at the same position. Additionally, this side etching also removes the first silicon nitride film 105 and the first silicon nitride film 105.
The ends of the pad oxide film 104 and the second silicon nitride film 107 become "eaves." Also, due to this groove formation,
The N-type epitaxial layer 103 has a first island region 103.
a and a second island region 103b are formed.

Next, after removing the first pad oxide film 104 under the "eaves", as shown in FIG. The oxide film 109 and the first polycrystalline silicon sidewall oxide film 110 are formed to a thickness of, for example, 200 to 1,000 mm, and the third silicon nitride film 111 is formed to a thickness of, for example, 500 to 1,000 mm using an LP (low pressure) CVD method or a plasma CVD method. 2,000 people will deposit it on the entire surface. These CVD methods have very good step coverage of the formed film, so as shown in FIG. The third silicon nitride film 111 can cover up to the third silicon nitride film 111.

After that, the third silicon nitride film 111 is formed by RIE method.
Perform anisotropic etching. The etching is stopped when the etching of the third silicon nitride film 111 is completed, that is, when only the bottom surface of the trench 10B is exposed as the second pad oxide film 109, as shown in FIG. 1(D).

At this point, as shown in FIG. 1(D), a second silicon nitride film 107 remains on the first polycrystalline silicon film 106, and a third silicon nitride film 11 remains on the side surface of the groove 10B.
1 will remain. Furthermore, the first polycrystalline silicon film 10
The third silicon nitride film 111 also remains on the side surface of 6. Such selective etching of the third silicon nitride film 111 is performed using the "eaves" portions of the first and second silicon nitride films 105 and 107 as a mask, without using a mask alignment process that would impede high integration. , can be done on Selfa Line.

Thereafter, an oxidation process is performed using the first silicon nitride film 105, the second silicon nitride film 107, and the third silicon nitride film 111 as masks, and an isolation oxide film 112 is formed in the groove portion as shown in FIG. 1(E). At this time, the oxide film grows to the bottom of the third silicon nitride film 111. Then, the third silicon nitride film 111 is lifted upward, and at the same time, the cross-sectional shape of the oxide film becomes nearly vertical. therefore,
In the original first and second island regions 103a and 103b, there is no intrusion of an oxide film such as a bird's beak, and no step difference such as a bird's head is formed. Further, since the third silicon nitride film 111 is also formed on the side surface of the first polycrystalline silicon film 106, the first polycrystalline silicon film 106 is not oxidized. Therefore, the first. Second island area 103a, 1
The positions of the side edges of 03b and the side surfaces of the first polycrystalline silicon film 106 are not affected by the thermal oxidation treatment for forming the isolation oxide film 112 and do not change.

Next, as shown in FIG. 1F, the third silicon nitride film 111, the second silicon nitride film 1o7. The first polycrystalline silicon film l06, the first polycrystalline silicon sidewall oxide film 110, and the first silicon nitride film 105 are all removed by photolithography.

Subsequently, by implanting phosphorus ions into the second island region 103b and performing heat treatment, the second island region 103b is transformed into an N'''' type buried diffusion layer, as shown in FIG. 1(G). 10
Deep collector region 1 for reducing collector resistance reaching 2
13, and a deep collector oxide film 11 thicker than the first pad oxide film 104 is formed on its surface by thermal oxidation.
Get 4.

Next, as shown in FIG. 1(G), the first island region 1
All of the third silicon nitride film 111 and second silicon nitride film 107 on 03a, the first silicon sidewall oxide film 110 and the first silicon in the portion not covered by the first polycrystalline silicon film 106 The nitride film 105 is removed, and on the first island region 103a,
An island pattern consisting of the first silicon nitride film 105 and the first polycrystalline silicon film 106 is formed.

Next, as shown in FIG. 1(H), the first island region 103
Using the island pattern on a as a mask, the portions of the first pad oxide film 104 that are not covered by the island pattern and the oxide film at the end of the isolation oxide film 112 are anisotropically etched to form the first island. The side edges of region 103a are exposed.

Subsequently, as shown in FIG. 1 (1), after depositing a second polycrystalline silicon film 115 of, for example, 2,000 to 5,000 layers over the entire surface, as shown in the same figure, the island area 1 is
A resist pattern 116 for planarization is formed so as to surround the convex portion on 03a. Subsequently, after applying resist again and flattening the resist surface, the second polycrystalline silicon film 115 and the first polycrystalline silicon film on the convex portion of the island region 103a are etched under conditions such that the etching rate of the resist and the polycrystalline silicon are equal. The crystalline silicon film 106 is first etched by anisotropic etching.
Etching is performed until the silicon nitride film 105 is exposed, and then the remaining resist is removed.

Through this step, the first polycrystalline silicon film 106 is completely removed as shown in FIG. It remains so as to extend from the first island region 103a.

Next, after the surface of the second polycrystalline silicon film 115 is thinly oxidized, boron ions are implanted into the second polycrystalline silicon film 115 at a dose of, for example, I~5×10 “cm−”. . Next, as shown in Figure 1 (κ〉),
The second polycrystalline silicon film 115 other than the base extraction electrode area is removed by photolithography.

Next, heat treatment is performed to form an inactive base region 117 in the first island region 103a by diffusion of boron from the second polycrystalline silicon film 115, as shown in FIG. A polycrystalline silicon oxide film 11B is formed on the surface of the second polycrystalline silicon film 115.

20 Next, the first silicon nitride film 1 on the I-th island region 103a is
After removing all of 05, CVD oxidation II! is applied to the entire surface by LPCVD as shown in FIG. 1(M). 119 is deposited.

Next, as shown in FIG. 1(N), CV
The D oxide film 119 is etched back to form sidewalls 119a of the CVD oxide film 119 on the side surfaces of the second polycrystalline silicon film 115 and the polycrystalline silicon oxide film 118. This sidewall 119a narrows the opening formed by the removal in the portion where the first silicon nitride film 105 on the first island region 103a is removed.

Then, the narrowed opening and the first pad oxide film 10
0.5 to 1 boron in the first island region 103a through 4
×lO14cIII-z ion implantation, 900~9
By performing annealing at a temperature of 50'C, the active base region 120 is formed in the first island region 103a so as to extend into the inactive base region 117, as shown in FIG. Form.

Next, the first pad oxide 111 on the active base region 120
104 and the deep collector oxide film 114, a third polycrystalline silicon film 121 of, for example, 3,000 to 5,000 layers is deposited on the entire surface as shown in FIG. 1(0).

Subsequently, after the surface of the third polycrystalline silicon film 121 is oxidized by about 200 layers, arsenic is ion-implanted into the third polycrystalline silicon film 121 to an amount of about l Q l 6 crtr - t. Thereafter, the third polycrystalline silicon film 121 is etched by photolithography to leave the third polycrystalline silicon film 121 as a collector electrode on the deep collector region 113 as shown in FIG. A vine electrode is left on the first island region 103a in the portion where the first silicon nitride film has been removed and its surrounding area. Thereafter, by performing heat treatment, the remaining third region on the first island region 103a is
Due to the diffusion of arsenic from the polycrystalline silicon IIl21, an ivy region 122 is formed in the active base region 120 as shown in FIG. 1(P). The element is now fully functional.

(Effects of the Invention) As described above in detail, according to the manufacturing method of the present invention, before forming the element isolation oxide film, the first By forming a third oxidation-resistant film on the side surface of the polycrystalline semiconductor layer, it is possible to avoid the formation of a bird's head with the polycrystalline semiconductor oxide film during the formation of the element isolation oxide film. It is possible to prevent the formation of a large step on the element isolation oxide ridge. As a result, even when forming metal electrode wiring layers and multilayer wiring, there is no reduction in wiring reliability due to disconnection defects or local thinning of the film, resulting in high yield, high reliability, and high performance semiconductor integrated circuit devices. can be obtained.

Furthermore, according to the present invention, the difference in pattern conversion during the formation of the element isolation oxide film is determined only by the amount of etching at the time of the groove shape of the semiconductor substrate, so compared to the previously proposed method in which bird's beaks are formed. This can be expected to have a significant effect on higher integration due to the reduction of the H area.

[Brief explanation of drawings]

FIG. 1 is a process sectional view showing an embodiment of the method for manufacturing a semiconductor integrated circuit device of the present invention, and FIG. 2 is a process sectional view showing a manufacturing method previously proposed by the present inventor. 101...P type semiconductor substrate, 103...N type epitaxial layer, l03a...first island region, 105
. . . first silicon nitride film, 106 . . . first polycrystalline silicon film, 107 . . . second silicon nitride film, 10B.
...Groove, 111...Third silicon nitride film, 112...
- Isolation oxide film, 115... second polycrystalline silicon film, 1
17... Inactive heath region, 118... Polycrystalline silicon oxide film, 119... CVD oxide film, 119a...
- Sidewall, 120...Active base region, 12
1... Third polycrystalline silicon film, 122... Emitter region.

Claims (2)

[Claims] (1) (a) Forming a three-layer film consisting of a first oxidation-resistant film, a first polycrystalline semiconductor layer, and a second oxidation-resistant film on a selected region of the semiconductor substrate surface; b) Forming a groove having an undercut under the first oxidation-resistant film in the exposed portion of the semiconductor substrate, and side-etching the first polycrystalline semiconductor layer to form a first polycrystalline semiconductor layer. (c) selectively forming a third oxidation-resistant film on the side walls of the trench and the side surfaces of the first polycrystalline semiconductor layer; (d) the first polycrystalline semiconductor layer; (e) forming an element isolation oxide film in the trench by selectively oxidizing the semiconductor substrate using the third oxidation-resistant film as a mask; (e) forming the second and third oxidation-resistant films; (f) removing the entire portion of the first oxidation-resistant film that is not covered with the first polycrystalline semiconductor layer; (f) the island of the semiconductor substrate surrounded by the element isolation oxide film; etching the element isolation oxide film using the first polycrystalline semiconductor layer and the first oxidation-resistant film above the region portion as a mask until a part of the island region is exposed. A method for manufacturing a semiconductor integrated circuit device. (2) In addition to the method for manufacturing a semiconductor integrated circuit device according to claim (1), (a) a second polycrystalline semiconductor layer is extended from the island region in contact with an exposed portion of the island region; (b) introducing impurities of a second conductivity type into the second polycrystalline semiconductor layer, and removing the first polycrystalline semiconductor layer on the island region; Due to the diffusion of the second conductivity type impurity from the semiconductor layer, an inactive base region of the second conductivity type is formed in a part of the island region of the first conductivity type, and an inactive base region of the second conductivity type is formed on the surface of the second polycrystalline semiconductor layer. (c) After removing the first oxidation-resistant film on the island region, the end side surface of the second polycrystalline semiconductor layer exposed in the removed portion and its (d) forming a sidewall of a second insulating film on the side surface of the end of the first insulating film; (d) doping an impurity of a second conductivity type into the island region through the removed portion narrowed by the sidewall; (e) introducing a third polycrystalline semiconductor doped with a first conductivity type impurity into the narrowed removed portion on the island region; forming a first conductivity type emitter region in the second conductivity type active base region by diffusion of the first conductivity type impurity from the third polycrystalline semiconductor layer. A method of manufacturing a semiconductor integrated circuit device, characterized by: