JPH0322463A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a malfunction by a construction wherein a conductor layer which is insulated by an oxide layer from a resistance formed of polycrystalline silicon or a gate or a wiring of an MOS transistor and a metal wiring and is connected to a power source or a grounding conductor on an integrated circuit is formed in a region wherein the resistance or the gate or the wiring intersects the metal wiring. CONSTITUTION:A semiconductor device is constructed by having an oxide silicon film 5 provided on the surface of a resistance layer 3 and covering the resistance layer 3, a polycrystalline silicon layer 6 provided on the oxide silicon film 5, an oxide silicon film 7 provided on the surface of the polycrystalline layer 6 and covering the polycrystalline silicon layer 6, a wiring 8 provided on the oxide silicon film 7 and intersecting the resistance layer 3, and a wiring 9 provided in connection with the polycrystalline silicon film 6 in an opening provided in the oxide silicon film 7. A capacitor C1 formed of the resistance layer 3 and the polycrystalline silicon film 6 through the intermediary of the oxide silicon film 5 and a capacitor C2 formed of the polycrystalline silicon layer 6 and the wiring 8 through the intermediary of the oxide silicon film 7 are connected to a power source or a grounding conductor by the wiring 9 so that a high-frequency signal be grounded, and thereby a signal of mutual leak between the resistance layer 3 and the wiring 8 is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device having cross wiring.

[Conventional technology]

As shown in FIG. 3, a conventional semiconductor device includes a resistor layer 3 made of a polycrystalline silicon layer selectively provided on a silicon oxide film 2 provided on a silicon substrate 1, and a resistor layer 3 on both ends of the resistor layer 3. It is constructed by having a wiring 8 which intersects with the resistance layer 3 via the connected wirings 4a and 4b and the silicon oxide 11!5 provided on the resistance layer 3. Here, as shown in FIG. 4, a capacitor C is constituted by the resistance layer 3 and the wiring 8 with the silicon oxide film 5 interposed therebetween.

[Problem to be solved by the invention]

The conventional semiconductor device described above uses an oxide film as a dielectric, and uses a resistive layer formed by a polycrystalline silicon layer and a capacitor whose poles are interconnections, so that interference occurs between the two. That is, there is a drawback that a signal induced by the coupling between the resistance layer and the wiring acts on a circuit connected to the resistance layer and the wiring, causing malfunction.

[Means to solve the problem]

The semiconductor device of the present invention has an integrated circuit which is insulated from the gate or wiring of a polycrystalline silicon transistor by an oxide film in the region where the wiring and the metal wiring intersect with each other. It has a conductive layer connected to a power or ground wire on top.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a sectional view of an embodiment of the present invention.

As shown in FIG. 1, a resistive layer 3 made of a polycrystalline silicon layer is selectively provided on a silicon oxide film 2 provided on a silicon substrate 1, and a resistive layer 3 is provided connected to both ends of the resistive layer 3. The wiring 4a and the wiring 4b, the silicon oxide film 5 provided on the surface of the resistance layer 3 and covering the resistance layer 3, the polycrystalline silicon layer 6 provided on the silicon oxide film 5, and the polycrystalline silicon layer 6.
a silicon oxide film 7 provided on the surface of the silicon oxide film 7 to cover the polycrystalline silicon layer 6; a wiring 8 provided on the silicon oxide film 7 to intersect with the resistance layer 3; A semiconductor device is configured by having a wiring 9 connected to the silicon layer 6.

FIG. 2 is an equivalent circuit diagram of the embodiment shown in FIG. A capacitor C formed of a resistive layer 3 and a polycrystalline silicon layer 6 via a silicon oxide film 5, and a capacitor C2 formed of a polycrystalline silicon layer 6 and a wiring 8 via a silicon oxide film 7 are connected to a power supply by a wiring 9. Alternatively, the high frequency signal is grounded by being connected to a grounding line, thereby preventing signals from leaking between the resistance layer 3 and the wiring 8.

Note that the same effect is obtained not only in the case of a resistive layer but also in the case of a gate electrode of a MOS transistor.

〔Effect of the invention〕

As explained above, in the present invention, when a resistor formed by a polycrystalline silicon layer or a gate of a MOS transistor intersects with a metal wiring, an oxide film is insulated between them, and the impedance on the integrated circuit is low. By forming another polycrystalline silicon layer that is biased at the highest or lowest potential of the power supply, the resistance formed by the polycrystalline silicon layer and the interference between the metal wiring are shielded by the polycrystalline silicon layer. This prevents unnecessary signals from being generated due to the intersection of a resistor or MOS transistor formed by a crystalline silicon layer or a wiring and a metal wiring and affecting circuit operation.

[Brief explanation of drawings]

1 is a sectional view of an embodiment of the present invention, FIG. 2 is an equivalent circuit diagram of the embodiment of FIG. 1, FIG. 3 is a sectional view of a conventional semiconductor device, and FIG. 4 is a sectional view of the embodiment of FIG. FIG. 2 is an equivalent circuit diagram of a semiconductor device. 1... Silicon substrate, 2... Silicon oxide film, 3.
... Resistance layer, 4a, 4b... Wiring, 5... Silicon oxide film, 6... Polycrystalline silicon layer, 7... Silicon oxide film, 8, 9... Wiring, C, C, , C2... capacitor.

Claims (1)

[Claims] In a semiconductor device having a wiring that intersects with a resistive layer or gate electrode provided on an insulating film provided on a semiconductor substrate, an insulating film is interposed between the intersecting regions of the resistive layer or the gate electrode and the wiring. What is claimed is: 1. A semiconductor device comprising a conductor layer provided on the ground and connected to a power source or a ground line.