JPH03225433A - Single-chip microcomputer - Google Patents

Abstract

PURPOSE:To suppress the runaway of a program due to a wrong instruction code by adding error detection information indicating that an error not be corrected to an instruction code and storing them, interrupting the execution of instructions at an instruction execution part in response to the error detection information, and actuating exceptional processing. CONSTITUTION:An instruction prefetch means 108 writes the instruction code which is inputted from an instruction queue input bus 106 and an uncorrectable error detection signal 107 in an instruction queue latch 109. Then when the instruction execution part 113 requires an instruction, the instruction code in an instruction queue latch 109 indicated by an instruction queue pointer 110 is outputted to an instruction queue latch output bus 112 and a corresponding uncorrectable error detection signal 107 is outputted to the instruction execution part 113. The instruction execution part 113 decodes the instruction code on the instruction queue output bus 112 and when the uncorrectable error detection signal 107 is '1', an instruction execution control part 113 interrupts the execu tion of instructions immediately, so that the exceptional processing for an uncorrectable error is actuated. Consequently, the runaway of the program due to a defect of error inspection data is precluded.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a single-chip microcomputer,
In particular, the present invention relates to a single-chip microcomputer equipped with an error correction function for correcting errors in instruction codes and data read from an electrically rewritable ROM (hereinafter referred to as PROM).

[Conventional technology]

Conventionally, a single-chip microcomputer with an error correction function that incorporates this type of PROM or the like performs only error correction by an error correction means, and has a configuration as shown in FIG. The PROM 301 stores instruction codes, data, and error check data necessary for error correction, and receives a FROM read signal RD3 applied from the bus control unit 315.
12 outputs the instruction code and data in response to the PROM address bus 311 and error check data to the correction input bus 302. The error correction means 303 corrects errors in the instruction code or data using the instruction code or data on the error correction input bus 302 and the test data.
The error-corrected instruction code or data is output to the instruction queue human bus 304.

The instruction prefetching means 305 includes an instruction queue latch 306 that stores the error-corrected instruction code input to the instruction queue human-powered bus 304 in units of one word in a first-in first-out method (hereinafter referred to as FIFO), and an instruction queue latch 306 that stores the instruction code input to the instruction queue human-powered bus 304 in a first-in, first-out method (hereinafter referred to as FIFO). The instruction queue output bus 3 consists of an instruction queue pointer 307 that indicates the read position of the queue, and an instruction queue control unit 308 that controls reading and writing of the instruction queue latch 306.
Outputs the instruction code for 09.

The instruction queue latch 306 is composed of 1 word x 4 stages,
The instruction code and data after error correction by the error correction means 303 are taken into the first stage of the instruction queue latch 306 by the instruction queue write signal QWR 313 from the instruction queue control unit 308, and the contents of the instruction queue latch 306 before writing the instruction queue are read. Shift one gear. The instruction queue interface 307 is composed of 1 bit x 5 stages, and only 1 bit is set at 1 time, and indicates the read position of the instruction queue. The contents of the instruction queue latch 306 at the stage indicated by the pointer 307 are output to the instruction queue output bus 309.

Next, the operation of a conventional microcomputer with built-in FROM and error correction function will be explained. The bus control unit 315 checks whether there is space in the instruction queue latch 306 using the instruction queue pointer 307, and if there is space,
The instruction code for the PROM 301 is read to start a cycle, and the instruction code and error check data are read from the PROM 301 and input to the error correction input bus 302 of the error correction means 303. The error correction means 303 performs error correction and sends the error-corrected instruction code to the instruction queue human-powered bus 3.
Output to 04. The instruction prefetching means 305 writes the error-corrected instruction code on the instruction queue bus 304 to the instruction queue latch 306. The instruction execution unit 310 receives the error-corrected instruction code output to the instruction queue output bus 309 and executes the instruction.

[Invention or problem to be solved]

In the conventional single-chip microcomputer with an error correction function that includes a built-in PROM, the error check data input to the error correction means becomes defective for some reason, and the error correction means outputs a different result. However, since the instruction execution unit executes the instructions that are 1% higher, the problem is that the program may run out of control.

An object of the present invention is to provide a single-chip microcomputer that can prevent a program from running out of control due to defective error check data.

[Means to solve the problem]

The single-chip microcomputer of the present invention includes an instruction execution means, a storage means for storing test data for error correction together with the instruction code and data of the instruction execution means, and a storage means for storing the test data for error correction. correction means for correcting the instruction code and the data according to the error and outputting error detection information when the correction is an error; Prefetching means for adding and storing detection information is provided, and the instruction execution means performs processing according to the error detection information.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. PROM10I stores instruction codes, data, and corresponding error check data necessary for error correction. FROM read signal RD1 from bus control unit 102
14, it receives an address from the bus control unit 102, and outputs the corresponding instruction code, data, and error check data to the error correction input bus 104.

The error correction means 105 detects errors in the data input from the error correction input bus 104 and corrects the errors in the instruction code or data accordingly.Then, the error corrected data is sent to the instruction queue manual bus. 106 and outputs "1" when the input data is defective and error correction is impossible, and "0" when no error is detected in the input data or when incorrect input data is correctly corrected. " is output as the error correction impossible detection signal 107.

The instruction prefetching means 108 receives the instruction code input from the instruction queue human power bus 106 and the error correction impossible detection signal 10.
Instruction queue latch 1 stores 7 in 1 word + 1 bit
0, an instruction queue pointer 110 indicating the read position of the instruction queue latch 109, and an instruction queue control unit 111.
It consists of

Instruction queue latch 109 is (1 word + 1 bit) x 4
The error correction means 105 adds an error correction impossibility detection signal 107 to the instruction code input from the instruction queue human power bus 106, which indicates whether the error correction was possible or not possible. The instruction queue write signal QWR115 is loaded into the first stage of the instruction queue latch 109, and the contents of the instruction queue launch before the instruction queue is written are shifted by one stage.

The instruction queue pointer 110 is composed of 1 bit x 5 stages, and only one bit is set to "1" to indicate the instruction queue read position. The contents of the instruction queue latch indicated by 110 are output to the instruction queue output bus 112.

Next, the operation will be explained. The bus control unit 102 checks whether there is space in the instruction queue latch 109 using the instruction queue pointer 110. If there is space, the bus control unit 102 starts an instruction code read cycle and outputs the output including the instruction code and error check data from the PROMl0I and corrects the error. Error correction input bus 104 of the means.

The error correction means 105 performs error correction on the instruction code input to the error correction input bus 104 and the error check data according to the error check data, and outputs the instruction code output after error correction to the instruction queue human power bus 106. At the same time, an error correction impossibility detection signal 107 indicating whether error correction was possible is output. Further, the instruction prefetching means 108 writes the instruction code and error correction impossible detection signal inputted from the instruction queue human power bus 106 to the instruction queue latch 109, and when the instruction execution unit 113 needs an instruction, The instruction code of the instruction queue latch 109 indicated by the pointer 110 is transferred to the instruction queue latch 109 from the instruction queue latch 109.
At the same time, the corresponding error correction impossibility detection signal 107 is output to the instruction execution unit 113. Instruction execution unit 1
13 decodes the instruction code on the instruction queue output bus 112, and the error correction impossible signal 107 is set to “1°”.
°, the instruction execution control unit 114 immediately interrupts the execution of the instruction and performs exception processing when error correction is not possible, such as displaying an external display indicating that error correction is not possible or performing other software processing. Start the process. Further, when the error detection signal 107 is "0°", the instruction of the read instruction code is executed as it is without activating exception processing.

FIG. 2 is a block diagram showing a second embodiment of the invention. In this embodiment, the error correction means 201 detects errors using error check data of data containing errors, performs error correction, and outputs the error-corrected output to the instruction queue manager 202, similar to the first embodiment. In addition to the normal operation, it is 1°' when there is an error in the data and error correction is possible, and it is The error correction execution detection signal 203 becomes ``O'', and it becomes ``1'' when there is an error in the data and the error cannot be corrected, and when there is no error in the data, and when there is an error in the data, it is an error. Error correction impossibility detection signal 204 becomes “0” when correction is possible.
It outputs two types of detection signals.

The instruction prefetching means 205 includes a latch for storing the error correction execution detection signal 203 when the error correction is possible, in addition to a latch for storing the error correction impossible detection signal 204 using the instruction queue latch 206 as the error correction detection information (1 word + 2 (bit) x 4 stages.

The instruction execution unit 208 has two types of exception handling: exception handling 1 for handling corrected data when error correction has been performed correctly, and exception handling 2 for handling error correction when it is impossible. , and has an exception handling permission flag 209 that allows exception handling 1. Exception handling permission flag 209
can be set/reset by command, and is set to 0 when reset.
°' masks execution of exception handling 1, and when "1'', execution of exception handling 1 is permitted.

Next, the operation will be explained. The PROM output includes error check data, and the error correction means 201 performs error correction on the output according to the error check data, outputs the error-corrected instruction code output to the instruction queue human power lotus 202, and outputs the error check result. Error correction execution detection signal 203 and error correction impossible detection signal 204 as error detection information for
Output.

The instruction prefetching means 205 stores the error-corrected instruction code output from the error correction means 201, the error correction execution detection signal 203, and the error correction impossible detection signal 204 in the instruction queue latch 206.

The instruction execution unit 208 outputs an instruction queue output from the instruction queue latch 206 indicated by the instruction queue pointer 207 of the instruction prefetching means 205, an error correction execution detection signal 203 which is error check information corresponding to the instruction queue output, and an error correction execution detection signal 203 which is error check information corresponding to the instruction queue output. Read signal 204 and detect error correction impossible detection signal 2
04 is "1", that is, when an error is detected but the error cannot be corrected, the instruction is immediately interrupted and exception handling 2 is activated. Also, the error correction execution detection signal 203 is "1", that is, when an error is detected and error correction is performed correctly.
Further, when the exception handling permission flag 209 is set by an instruction and the set state is "1 pa", exception handling 1 is activated.

Further, when no error is detected, or when the exception processing permission flag 209 is in the reset state "0°," the exception processing 1 is not activated and the instruction is executed as is.

In this embodiment, a latch for storing an error correction execution detection signal indicating that an error has been detected and error correction has been correctly performed is added to the instruction prefetching means, and an exception processing execution permission flag is provided in the instruction execution means. You can choose to activate exception handling when an error is detected and corrected.

〔Effect of the invention〕

As explained above, in the present invention, when an instruction code is prefetched,
Error detection information indicating whether error correction was performed correctly or an error was detected but error correction was not possible is added to the instruction code and stored, and the instruction execution unit executes the instruction in response to the error detection information. By having a means to interrupt execution and start exception handling, it is possible to execute processing for an erroneous instruction code immediately before an instruction with an uncorrectable instruction code is executed, which has the effect of suppressing program runaway due to an erroneous instruction code. There is.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention;
The figure is a block diagram showing a second embodiment of the present invention, and FIG. 3 is a block diagram showing a conventional example. 101...PROM, 102...Bus control unit, 10
3... PROM address, 104... error correction input bus, 105... error correction means, 106... instruction queue human power lot, 107... error correction impossible detection signal,
108... Instruction prefetching means, 109... Instruction queue latch, 11.0... Instruction queue pointer, 111.
... Instruction queue control unit, 112... Instruction queue output bus, 113... Instruction execution unit, 114... PROM read signal RD, 115... Instruction queue write signal QWR5116... Instruction queue read signal QRD ,
201...Error correction means, 202...Instruction queue human power bus, 203...Error correction execution detection signal, 204...
...Error correction impossible detection signal, 205...Instruction prefetching means, 206...Instruction queue latch, 207...Instruction queue output bus, 208...Instruction execution unit, 209...
...Exception handling 1 permission flag, 301...PROM, 3
02...Error correction input bus, 303...Error correction means, 304...Instruction queue bus, 305...Instruction prefetching means, 306...Instruction queue latch, 307
...Instruction queue pointer, 308...Instruction queue control unit, 309...Instruction queue output bus, 310...
Instruction execution unit, 311... PROM address bus, 31
2...PROM read signal RD, 313...Instruction queue write signal QWR5314...Instruction queue read signal QRD, 315...Bus control unit.

Claims (1)

[Claims] an instruction execution means; a storage means for storing check data for error correction together with the instruction code and data of the instruction execution means; and correction of the instruction code and the data according to the check data for error correction. a correction means for outputting error detection information when the correction is an error; and a prefetching means for adding and storing the error detection information to the instruction code and the data before the instruction execution means executes the instruction. A single-chip microcomputer, characterized in that the instruction execution means performs processing according to the error detection information.