JPH07105000A - Fetch error control device - Google Patents

Abstract

(57) [Summary] (Modified) [Purpose] When an instruction fetch error is detected in a central processing unit (CPU) that performs instruction fetch and execution in parallel in a pipeline manner, the pipeline operation of the CPU Retry instruction fetch at high speed without stopping. When an instruction fetch error is detected, the error detection means 54 determines whether or not the instruction execution by the instruction execution means 56 should be stopped, and outputs an error signal 57 to the fetch error counting means 55. At this time, the retry control means 51 sends the instruction address of the instruction in which the fetch error is detected to the address bus 4 again to retry the fetch. Further, the instruction changing means 53 immediately changes the fetched instruction code to another instruction code and sends it to the instruction executing means 56. The instruction executing means 56 executes the other instruction code sent in place of the fetched instruction code. The fetch error counting means 55 counts the number of times the error signal 57 is output, and when the count value exceeds a certain value, the process proceeds to the abnormal processing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control system for a central processing unit used in a computer, a controller, etc., and more particularly to a fetch error control device for a microcomputer.

[0002]

2. Description of the Related Art In various information processing apparatuses such as computers and controllers, improving the reliability and stability of processing by a central processing unit (CPU) has always been a major issue, and various techniques have been introduced for that purpose. It was CP
One of them is a fetch error monitoring technique for monitoring on the bus whether or not the instruction code to be executed has been correctly read from the program memory in order to prevent the U from malfunctioning when the instruction is executed.

Generally, an instruction fetch error detection mechanism such as a parity check mechanism and a bus transfer time monitoring mechanism is provided outside the CPU, and when a fetch error is detected, an abnormality detection signal is output to the CPU. Has been.

In a conventional CPU, when an abnormality detection signal is received from an instruction fetch error detection mechanism outside the CPU, an exception process such as an interrupt or a trap is immediately generated to perform a fetch retry process, that is, a fetch retry process. ing.

FIG. 12 shows the internal structure of a conventional CPU. The CPU of FIG. 12 has a pipeline structure in which the instruction fetch unit 11 and the instruction execution unit 21 perform processing in parallel,
An address bus 16 and a data bus 17 are connected to a program memory not shown in FIG. Abnormality detection signal 1
8 is output from the instruction fetch error detection mechanism that monitors the instruction code on the data bus 17.

In the instruction fetch unit 11, first, the instruction address of the fetched instruction stored in the fetch program counter register 14 is output to the address bus 16. Next, the instruction code fetched from the program memory according to this instruction address is fetched via the data bus 17 into the fetch instruction register 1
Taken in 5. Then, the fetch program counter register 14 transfers the instruction address to the address update counter 1
3 and the execution program counter register 22 in the instruction execution unit 21, and the fetch instruction register 15 sends the fetched instruction code to the execution instruction register 23 in the instruction execution unit 21.

In the instruction execution unit 21, the instruction executor 2
Reference numeral 4 fetches the instruction address and instruction code delivered from the instruction fetch unit 11 from the execution program counter register 22 and the execution instruction register 23, respectively, and executes instruction execution processing. In the case of a control / arithmetic instruction, the instruction is executed with reference to the register file 25. If the executed instruction is a branch instruction, the branch instruction detection signal 27 is set to logic “1”, and the branch destination address 26 described in the branch instruction is sent to the multiplexer 12 of the instruction fetch unit 11. Output.

The multiplexer 12 receives the branch instruction detection signal 2
When 7 is a logic "0", the instruction address incremented by the address update counter 13 is selected and set in the fetch program counter register 14, and when the branch instruction detection signal 27 is a logic "1", the branch destination address is selected. 26 is selected and set in the fetch program counter register 14.

When an abnormality is detected in the fetched instruction code by the instruction fetch error detection mechanism, the abnormality detection signal 18 becomes logic "1" and the instruction execution unit 24 is immediately notified of the abnormality detection. . In response to this, the instruction executor 24 temporarily suspends the execution of the instruction to stop the pipeline operation, generates an exception process such as an interrupt or a trap to fetch the abnormal instruction again, and then performs the fetch retry. Invoke the routine.

FIG. 13 is a flow chart showing an example of this fetch retry routine. When the exception process occurs, the cause of the occurrence is first checked in step S101 of FIG. If the cause of the exception process is a fetch error (S102, YES), the retry counter is incremented in S103, and if it is another factor (S102, NO), the process proceeds to another error process (S107).

Next, in S104, it is checked whether the value of the retry counter has reached a certain number of times, and when the retry counter counts up (S10
4, YES), assuming that the fetch error has occurred a certain number of times consecutively, giving up the instruction fetch retry,
The operation of the PU is stopped (S108). If the retry counter is not counting up (S104, NO),
In S105, the fetch instruction register 15 and the execution instruction register 23 are cleared to discard the fetched instruction code, and subsequently in S106, the same instruction address is set in the fetch program counter register 14, and then the normal program processing is resumed. .

As described above, in the conventional CPU, the retry of the instruction fetch when the fetch error is detected is
It is performed by a fetch retry routine such as an interrupt or trap.

[0013]

However, the conventional C
The instruction error fetch error control method in the PU has the following problems. (1) In order to set the same instruction address again in the fetch program counter register to refetch an abnormal instruction, the CPU must stop other processing and generate exception processing. Processing time is required. (2) Also, in order to erase an abnormal instruction from the fetch instruction register and the execution instruction register, the CPU must also generate an exception process, which requires a lot of processing time. (3) Since exception processing is generated each time a fetch error is detected, if fetch errors occur continuously, the processing of FIG. 13 will be repeated many times, and the processing time will increase in proportion to the number of occurrences. To do. Actually, a predetermined number of fetch retries are continuously executed,
Even if the normal instruction code cannot be fetched, it is desirable that the CPU causes exception processing.

Further, in order to perform such complicated control for fetch retry by the exception processing routine, the user needs to construct the processing procedure by a program.

Some CPUs control all of these series of processing by microcode, but the CPU must suspend the processing of the instruction fetch unit and the instruction execution unit during the execution thereof. There are also problems that require a lot of latency as well.

In the fetch error control method as described above, pipeline multi-stage technology and RISC architecture (Reduced Instruct), which have been actively introduced in recent years.
ionSet Computer Architecture) microcodeless technology cannot be effectively dealt with.

An object of the present invention is to disturb the pipeline operation of the CPU when an instruction fetch error is detected,
An object of the present invention is to provide a fetch error control device capable of retrying instruction fetch at high speed without stopping the processing.

[0018]

FIG. 1 is a block diagram showing the principle of a central processing unit (CPU) having a fetch error control device according to the present invention. In FIG. 1, the CPU 1 is connected to an external program memory via an address bus 4 and a data bus 5.

The present invention is a fetch means 52 for storing an instruction input from the program memory via the data bus 5.
And a fetch execution control unit 56 for executing the instruction stored in the fetch unit 52, and a fetch error control device in the CPU 1 having a pipeline structure for processing the fetch of the instruction and the execution of the fetched instruction in parallel. There
The error detection means 54, the retry control means 51, the instruction change means 53, and the fetch error counting means 55 are provided.

When the error detection means 54 is notified by the fetch error detection signal 6 that an instruction fetch error has been detected, the error detection means 54 determines whether or not the instruction execution means 56 should stop the instruction execution, and stops the instruction execution. If you should,
The error signal 38 is output to the fetch error counting means 55.

At this time, the retry control means 51 outputs the address of the instruction in which the fetch error has occurred to the address bus 4 again, and fetches the instruction from the program memory again.

At this time, the instruction changing unit 53 replaces the instruction fetched and stored in the fetch unit 52 with the fetch error with another instruction which does not immediately affect the operation of the instruction executing unit 56. The instruction is changed and output to the instruction executing means 56, and the instruction executing means 56 executes other instruction which is the changed instruction.

The fetch error counting means 55 counts the number of times the error signal 57 is output from the error detecting means 54,
When the count value exceeds a certain value, the exception processing signal 58 is output to the instruction executing means 56. Instruction executing means 56
When the exception processing signal 58 is received, the instruction execution is stopped and exception processing for abnormal processing is generated.

[0024]

When the fetch error detection signal 6 notifies the CPU of the occurrence of an instruction fetch error, the error detection means 54 determines whether or not to stop the execution processing of the instruction execution means 56, so the execution is stopped. When it is not necessary to execute it, the instruction executing means 56 can continue the execution processing.

When an instruction fetch error occurs,
In order to fetch the instruction in which the fetch error is detected again, the retry control means 51 automatically sends the instruction address of the instruction to the address bus 4. Therefore, the operation of the instruction executing means 56 for refetching the instruction. Never stop.

At this time, the instruction executing means 56 executes another instruction which is changed by the instruction changing means 53 and does not affect the execution operation, so that the execution error due to the execution of the instruction having the fetch error does not occur. In addition, while continuing the pipeline operation, it is possible to wait until the fetch retry succeeds.

Further, the fetch error counting means 55 counts the number of times the error signal 57 is output, and when the number of times exceeds a predetermined fixed number, it outputs an exception processing signal 58. The instruction execution means 56 receives the exception processing signal 58, generates exception processing such as interrupts and traps, and executes abnormality detection processing. In this way, when fetch errors occur continuously, exception processing is performed after fetch retry is performed a fixed number of times. Therefore, the pipeline operation of the CPU 1 is stopped while fetch fetch is continuously performed. You don't have to.

[0028]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 shows an instruction fetch error detection mechanism by parity check. CPU1 in FIG.
Is connected to the program memory 2 by an address bus 4 and a data bus 5, and a parity check mechanism 3 is connected on the data bus 5. The CPU 1 outputs the address of the instruction code to be fetched onto the address bus 4, and fetches the instruction code from the program memory 2 via the data bus 5. At this time, the parity check mechanism 3 monitors the parity of the instruction code fetched on the data bus 5, and outputs a fetch error detection signal 6 to the CPU 1 when a parity abnormality is detected. The CPU 1 is informed by the fetch error detection signal 6 that the instruction code fetched on the data bus 5 is abnormal.

FIG. 3 is a block diagram of a CPU of an embodiment using the fetch error control device of the present invention. CPU in Figure 3
Has a pipeline structure including two stages of an instruction fetch unit 31 that fetches an instruction and an instruction execution unit 41 that executes the fetched instruction, and significant processing is executed in parallel.

Further, the instruction fetch unit 31 uses the address bus 4
2 is connected to the program memory 2 of FIG. 2 by a data bus 5 and the instruction code output from the program memory 2 onto the data bus 5 is monitored by a fetch error detection mechanism such as the parity check mechanism 3 of FIG. There is. When the fetch error detection mechanism detects a fetch error in this instruction code, it sets the fetch error detection signal 6 to logic "1" and outputs it to the CPU 1.

In FIG. 2, the parity check mechanism 3 provided outside the CPU 1 is used as the instruction fetch error detecting means. However, this may be provided inside the CPU 1 or the fetch error detection other than the parity check mechanism 3 is detected. It is also possible to use a mechanism. Also in these cases, when a fetch error is detected, the fetch error detection signal 6 is set to logic "1".

The instruction fetch unit 31 of FIG. 3 is composed of a fetch program counter register 33, a fetch instruction register 34, an error detection circuit 36, a retry control circuit 32, an instruction rewriting circuit 35 and a fetch error counting circuit 37, and executes an instruction. The unit 41 is composed of an execution program counter register 42, an execution instruction register 43, an instruction executor 44, and a register file 45.

The instruction fetch unit 31 and the instruction execution unit 4 shown in FIG.
1, the execution program counter register 42, the execution instruction register 43, and the instruction executor 44 form a fetch error control device. The retry control circuit 32 and the fetch program counter register 33 of the instruction fetch unit 31 correspond to the retry control means 51 of FIG. 1, and the fetch instruction register 34 is the fetch means 52.
Corresponding to. The instruction rewriting circuit 35, the error detecting circuit 36, and the fetch error counting circuit 37 correspond to the instruction changing means 53, the error detecting means 54, and the fetch error counting means 55, respectively. The instruction executing section 41 corresponds to the instruction executing means 56.

The fetch error detection signal 6 output from the fetch error detection mechanism is input to the error detection circuit 36, the retry control circuit 32, and the instruction rewriting circuit 35. The fetch program counter register 33 of the instruction fetch unit 31 sends the stored instruction address of the instruction to be fetched to the address bus 4, and the fetch instruction register 34 is fetched according to the instruction address sent from the fetch program counter register 33. , And stores the instruction code input from the data bus 5.

Fetch program counter register 33
Also sends the instruction address to the retry control circuit 32 and the execution program counter register 42 in the instruction execution unit 41, and the retry control circuit 32 performs the fetch retry when the fetch error detection signal 6 is logic "1". Then, the instruction address sent from the fetch program counter register 33 is returned to the fetch program counter register 33 again.

Fetch instruction register 34
Sends the fetched instruction code to the execution instruction register 43 in the instruction executing section 41 via the instruction rewriting circuit 35. Fetch error detection signal 6 is logic "1"
At this time, the instruction rewriting circuit 35 does not send the instruction code input from the fetch instruction register 34 to the execution instruction register 43, but instead sends the other instruction code stored in the instruction rewriting circuit 35.

The instruction executor 44 of the instruction executor 41 retrieves an instruction address and an instruction code from the execution program counter register 42 and the execution instruction register 43, and executes the instruction code. At this time,
Data is taken out from the register file 45 as necessary, and the calculation result and the like are stored in the register file 45. When the executed instruction is a branch instruction, the branch destination address 61 is output to the retry control circuit 32, and the branch instruction detection signal 62 is set to logic "1" to set the retry control circuit 32.
To the error detection circuit 36.

The error detection circuit 36 uses the values of the fetch error detection signal 6 and the branch instruction detection signal 62 to determine the instruction execution unit 4
If it is determined that the execution processing of 1 should be stopped, the error signal 38 is set to logic "1", and the fetch error counting circuit 3
Send to 7.

The fetch error counting circuit 37 includes the CPU 1
1 signal outside the lead input from

[0040]

[Outer 1]

In synchronization with 63, the number of times the error signal 38 becomes logic "1" is counted, and when the count value reaches a predetermined constant value, the exception processing signal 39 is set to logic "1". Output to the instruction executor 44. When the exception processing signal 39 becomes logic "1", the instruction executor 44 stops the instruction execution processing, causes exception processing, and shifts to abnormal processing.

An embodiment of the error detection circuit 36 shown in FIG. 3 will be described with reference to FIGS. Figure 3
Error detection circuit 36 of the instruction execution unit 41 based on the values of the fetch error detection signal 6 and the branch instruction detection signal 62.
Determine whether to stop the execution of the instruction code by
If it should be stopped, the error signal 38 is output as logic "1" to the fetch error counting circuit 54.

FIG. 4 is a flow chart for explaining the operation of one embodiment of the error detection circuit 36. Step S in FIG.
At 151, the error detection circuit 36 first determines the value of the fetch error detection signal 6. When the fetch error detection signal 6 is logic "0", it is not necessary to stop the processing of the instruction executor 44, so the error signal 38 is set to logic "0".
Is set (S154).

When the fetch error detection signal 6 is logic "1", the value of the branch instruction detection signal 62 is determined in S152. If the branch instruction detection signal 62 is logic "1", the control of the instruction executor 44 shifts to the address of the branch destination, and the instruction code following the fetched branch instruction is not executed. Nevertheless, there is no danger of an execution error. Therefore, since it is not necessary to stop the execution of the instruction, the error signal 38 is set to logic "0" (S154).

The fetch error detection signal 6 is logic "1".
And the branch instruction detection signal 62 is logic "0",
Since the instruction code executed by the instruction executor 44 is not normal and an execution error may occur, the error signal 38 is set to logic "1" (S153).

The error detection circuit 36 performing such an operation
An example of this is shown in FIG. The error detection circuit 36 of FIG.
Is the logical product of an inverter 71 that inverts and outputs the value of the branch instruction detection signal 62 from the instruction executor 44, and the output of the inverter 71 and the fetch error detection signal 6,
The AND gate 72 outputs the error signal 38.

The output of the AND gate 72, that is, the error signal 38, is obtained when the fetch error detection signal 6 is logic "1",
And when the branch instruction detection signal 62 is logic "0", that is, when a fetch error is detected in the fetched instruction code and the previously executed instruction is not a branch instruction, it becomes logic "1". In the case of, the logical value is “0”. Therefore, even if a fetch error occurs, if the previously executed instruction is a branch instruction, the fact that a fetch error has occurred cannot be notified to the fetch error counting circuit 37. Do not count fetch errors as errors.

Next, an embodiment of the retry control circuit 32 shown in FIG. 3 will be described with reference to FIGS. The retry control circuit 52 of FIG. 3 generates an address of an instruction to be fetched next according to the values of the fetch error detection signal 6 and the branch instruction detection signal 62.

FIG. 6 is a flow chart for explaining the operation of the retry control circuit 32 shown in FIG. Step S20 of FIG.
1, the retry control circuit 32 first determines the instruction executor 4
It is determined whether the branch instruction detection signal 62 from 4 is logic "1", and if it is logic "1", the branch destination instruction needs to be fetched next. Is output to the fetch program counter register 33 (S204).

When the branch instruction detection signal 62 is logic "0", it is determined in step S202 whether the fetch error detection signal 6 is logic "1". If the fetch error detection signal 6 is logic "0", the instruction address of the instruction following the program is output to the fetch program counter register 33 (S203). If the fetch error detection signal 6 is logic "1", the instruction address from the fetch program counter register 33 is re-output as it is to the fetch program counter register 33 without updating the instruction address in order to fetch the instruction code. S205).

The retry control circuit 32 which performs such an operation
An example of this is shown in FIG. The retry control circuit 32 of FIG.
Selects either the address update counter 74 that increments and outputs the instruction address from the fetch program counter register 33, the instruction address from the fetch program counter register 33, the output of the address update counter 74, or the branch destination address 61. It is comprised from the multiplexer 73 which outputs.

When the fetch error detection signal 6 and the branch instruction detection signal 62 are both logic "0", the multiplexer 73 outputs the instruction address updated by the address update counter 74 as the instruction address of the subsequent instruction.
When the branch instruction detection signal 62 is logic "1", the instruction code that has already been fetched is automatically invalidated, so that the branch destination address 61 is output regardless of the value of the fetch error detection signal 6. The branch instruction detection signal 62 is logic "0" and the fetch error detection signal 6 is logic "1".
In the case of, the instruction address from the fetch program counter register 33 is output as it is in order to perform the fetch retry of the instruction code in which the error is detected.

The output of the multiplexer 73 is stored in the fetch program counter register 33 and then used as an instruction address in the address bus 4 when the next instruction is fetched.
Is output to.

Next, one embodiment of the instruction rewriting circuit 35 shown in FIG. 3 will be described with reference to FIGS. The instruction rewriting circuit 35 shown in FIG. 3 receives the fetch error detection signal 6, rewrites the instruction code input from the fetch instruction register 34, and sends it to the execution instruction register 43.

FIG. 8 is a flow chart for explaining the operation of the instruction rewriting circuit 35 of FIG. Step S21 of FIG.
1, the instruction rewriting circuit 35 determines whether or not the fetch error detection signal 6 is logic "1". If it is logic "1", the instruction code in which the error is detected from the fetch instruction register 34 is discarded, and Then, another instruction code that does not affect the operation of the instruction executor 24 is output to the execution instruction register 43 (S213). If the fetch error detection signal 6 is logic "0", the instruction code from the fetch instruction register 34 is normal, and is output to the execution instruction register 43 as it is (S21).
2).

The instruction rewriting circuit 35 performing such an operation.
An example of this is shown in FIG. The instruction rewriting circuit 35 of FIG.
Is an instruction rewriting register 75 in which an instruction code for rewriting is stored in advance, an instruction code output from the instruction rewriting register 75, or an instruction code input from the fetch instruction register 34 is selected and output. It is composed of a multiplexer 76.

The instruction rewriting register 75 stores an instruction code which does not affect the operation of the instruction executor 44, for example, a no operation code (NOP code). The multiplexer 76 receives the fetch error detection signal 6
Is logical "0", the instruction code input from the fetch instruction register 34 is output as it is, and when the fetch error detection signal 6 is logical "1",
The instruction code stored in the instruction rewriting register 75,
For example, a NOP code is output.

The output of the multiplexer 76 is stored in the execution instruction register 43. At this time, the instruction address stored in the fetch program counter register 33, that is, the instruction code input from the fetch instruction register 34, is stored in the execution program counter register 42. The instruction address corresponding to is stored.

The instruction executor 44 reads the instruction address of the execution program counter register 42, interprets the instruction code stored in the execution instruction register 43 as the instruction code fetched from the program memory 2, and executes it. If this is a NOP code, nothing is actually done, so that it does not affect the program processing by the instruction executor 44. Therefore, even if a fetch error occurs, the instruction executor 44 does not stop the processing, and when the next fetch retry succeeds, the instruction code that has been refetched continuously can be executed.

In FIG. 3, the instruction rewriting circuit 35 is connected between the fetch instruction register 34 and the execution instruction register 43. However, the present invention is not limited to this, and the instruction rewriting circuit 3
5 can also be provided elsewhere in the CPU. For example, the instruction rewriting circuit 35 may be connected between the execution instruction register 43 and the instruction executor 44 to rewrite the instruction code output from the execution instruction register 43.

Finally, an embodiment of the fetch error counting circuit 37 of FIG. 3 will be described with reference to FIGS. The fetch error counting circuit 37 of FIG. 3 counts the number of times that the error signal 38 from the error detection circuit 36 continuously becomes a logic “1”, and when it reaches a certain number, an exception is issued to the instruction executor 44. The processed signal 39 is output.

FIG. 10 is a flow chart for explaining the operation of the fetch error counting circuit 37. In step S221 of FIG. 10, the fetch error counting circuit 37 determines whether the error signal 38 is logic "1". If the error signal 38 is logic "0", it is not necessary to stop the processing of the instruction executor 44, so the count value is cleared (S22).
5), exception processing signal 39 is set to logic "0" (S2)
26). If the error signal 38 is logic "1", the count value is incremented (S222).

In step S223, the fetch error counting circuit 54 determines whether or not the count value has reached a preset constant value. When fetch errors for the same instruction occur successively and the count value of the fetch errors reaches a certain value, the exception processing signal 39 is set to logic "1" in order to request the exception processing from the instruction executor 44. Yes (S224). If the count value has not reached the fixed value, the process returns to step S221.

FIG. 11 shows an embodiment of the fetch error counting circuit 37 which performs such an operation. The fetch error counting circuit 37 of FIG. 11 is a clock synchronous type counter 77.
The error signal 38 is input to the count terminal (CNT) and the clear terminal 2 of the counter 77,
The exception processing signal is output from the output terminal (OUT).

[0065]

[Outside 2]

The external terminal 3 signal 63 generated by the instruction executor 44 is input to the clock terminal (CLK) of the counter 77 as a synchronous clock. Outside 4 signal 63

[0067]

[Outside 3]

[0068]

[Outside 4]

Is a signal for instruction fetch used by the CPU 1 to fetch an instruction code from the program memory 2 and store it in the fetch instruction register 34.

Error signal 38 input to the count terminal
Is counted by the RD signal 63. When the error signal 38 is logic "0", the count value is cleared by the clear terminal, and the exception processing signal 39 is logic "0". When the count value reaches a predetermined constant value, for example, three times, the exception processing signal 39 becomes logic "1". In response to this, the instruction executor 44 stops the execution process and causes an exception process.

It is needless to say that the predetermined constant value is not limited to three times and can be any value. Further, by providing the counter 77 with a counting upper limit value setting mechanism, the exception processing signal 39 is set to logic "1".
A configuration is also possible in which the constant count value is set to be programmable.

In FIG. 4 and FIG. 5, when the branch instruction detection signal 62 is logic "1", the fetch error detection signal 6
Has a logic "1", the count value of the fetch error counting circuit 54 is not incremented. However, the present invention is not limited to this, and by directly inputting the fetch error detection signal 6 as the error signal 38 to the fetch error counting circuit 54, the data bus 5
A configuration is possible in which the count value is incremented each time a fetch error is detected in the above instruction code. When such an error detection circuit is used, exception processing occurs more frequently than in the embodiments of FIGS.

[0073]

According to the fetch error control circuit of the present invention, when an error occurs in the instruction fetch by the CPU, C
The instruction fetch retry operation can be performed at high speed without stopping the PU instruction fetch cycle or instruction execution cycle or disturbing the pipeline operation inside the CPU.

When the retry of the instruction fetch is not successful due to a fatal abnormality or the like, the instruction execution unit can be notified of this and exception processing for the abnormal processing can be generated.

[Brief description of drawings]

FIG. 1 is a principle block diagram of a fetch error control device of the present invention.

FIG. 2 is a diagram showing a fetch error detection mechanism.

FIG. 3 is a configuration diagram of a CPU using a fetch error control device according to an embodiment of the present invention.

FIG. 4 is a flowchart showing the operation of the error detection circuit of the present invention.

FIG. 5 is an example of an error detection circuit.

FIG. 6 is a flowchart showing the operation of the retry control circuit of the present invention.

FIG. 7 is an example of a retry control circuit.

FIG. 8 is a flowchart showing the operation of the instruction rewriting circuit of the present invention.

FIG. 9 is an example of an instruction rewriting circuit.

FIG. 10 is a flowchart showing the operation of the fetch error counting circuit of the present invention.

FIG. 11 is an example of a fetch error counting circuit.

FIG. 12 is a configuration diagram of a CPU in a conventional example.

FIG. 13 is a flowchart showing processing of a fetch retry routine.

[Explanation of symbols]

 1 Central Processing Unit (CPU) 2 Program Memory 3 Parity Check Mechanism 4, 16 Address Bus 5, 17 Data Bus 6 Fetch Error Detection Signal 11, 31 Instruction Fetch Unit 12, 73, 76 Multiplexer 13, 74 Address Update Counter 14, 33 Fetch program counter register 15, 34 Fetch instruction register 18 Abnormality detection signal 21, 41 Instruction execution unit 22, 42 Execution program counter register 23, 43 Execution instruction register 24, 44 Instruction executor 25, 45 Register file 26, 61 Branch destination address 27, 62 Branch instruction detection signal 32 Retry control circuit 35 Instruction rewriting circuit 36 Error detection circuit 37 Fetch error counting circuit 38, 57 Error signal 39, 58 Exception processing signal 1 retry control means 52 fetches means 53 command change means 54 error detection unit 55 fetches the error counting means 56 instruction execution unit 63 RD signal 71 inverter 72 the AND gate 75 an instruction of rewriting the register 77 counter

Claims (4)

[Claims] 1. A fetch means (52) for storing an instruction input from a data bus (5), and the fetch means (5).
Instruction executing means (56) for executing the instruction stored in 2)
In the central processing unit (1) having the following, when the instruction fetch error detection signal (6) notifies that the instruction fetch error is detected, it is determined whether or not the instruction execution means (56) should stop the instruction execution. If the instruction execution is to be stopped, the fetch error control device is provided with an error detection means (54) for outputting an error signal (57) to the instruction execution means (56). 2. A retry for outputting the address of the instruction again to the address bus (4) when notified of the detection of the instruction fetch error by the fetch error detection signal (6), and fetching the instruction again. The fetch error control device according to claim 1, further comprising a control means (51). 3. When the fetch error detection signal (6) notifies the detection of an instruction fetch error, the fetched instruction stored in the fetch means (52) is immediately transferred to another instruction. An instruction changing means (53) for changing and outputting to the instruction executing means (56) is provided, and the instruction executing means (56) is the instruction changing means (53).
2. The fetch error control device according to claim 1, wherein the other instruction input by the other is executed. 4. The instruction execution means (56), which counts the number of times the error signal (57) is output from the error detection means (54), and when the count value of the output times exceeds a certain value. A fetch error counting means (55) for outputting an exception processing signal (58) is provided between the error detecting means (54) and the instruction executing means (56), and the instruction executing means (56) includes: The exception handling signal (58)
2. The fetch error control device according to claim 1, wherein the instruction execution process is stopped when the fact that the count value of the output count exceeds a certain value is notified by.