JPH03225460A - Multi-processing system - Google Patents

Abstract

PURPOSE:To use existing software as it is and to prevent a load applied on an operating system by attaching a conversion table which converts a logic address consisting of a name and a memory address proper to a processor into the physical address of a shared memory on a bus control part. CONSTITUTION:The timing of the processors P1-Pn to use a memory CM is executed asynchronously, and it is executed in such a way that the bus use request signals of the processors P1-Pn are transferred to the bus control part BC, and bus use permission signals are received from the bus control part BC, and access to the shared memory CM is performed with the memory access timing of each processor to a common bus CB. In such a way, the bus control part BC supplies the right in use of the common bus CB at every memory access of each processor to the processor, and simultaneously, converts the name and address proper to the processor outputted from each of the processors P1-Pn into the address on the shared memory CM. Thereby, it is possible to use the existing software as it is, and to prevent the load applied on the operating system.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a compound computer system, and particularly to a memory sharing device.

[Conventional technology]

In recent years, research has been conducted in various places to develop computer systems with excellent cost performance by combining multiple computers, and the results are highly anticipated. In computer complex systems, in addition to the problems of how computers are connected and the scheduling of tasks, the issue of how to effectively use memory, input/output devices, etc. is also an important point. The advantages of a computer complex system using a common bus are that the cost of attached hardware is relatively low and the system is highly expandable. In particular, memory sharing in a multiprocessor system is an extremely important issue that greatly affects the processing ability and reliability of the entire system, including synchronization processing, exclusive processing, and data sharing between processors. The problem here is that when multiple processors use one shared memory at the same time, efficient memory allocation is required to avoid conflicts with the address spaces of other processors.

[Problem that the invention seeks to solve]

Conventionally, this type of method has either had an address translation table corresponding to each of a plurality of 70 setters on a common bus, or had a common address translation table and used software for each processor or an operating system that manages the entire system. It was common to perform memory management. These methods have the drawback of placing a burden on the software or operating system of each processor, reducing the throughput of the entire system.

The purpose of the present invention was made in view of the various drawbacks mentioned above, and it is an object of the present invention to take full advantage of the effectiveness of a computer complex system based on a common bus coupling method, and to create a comparative system in which conventional software can be used as is and does not place any burden on the operating system. It provides a complex computer system that can be realized with simple hardware.

[Means for solving problems]

The present invention connects a plurality of processors and a shared memory that can be accessed by the processors in parallel via a common bus, and the common bus provides memory access to the address space of the shared memory of the processors to the processors. In a complex computer system, a bus control unit that grants the right to use the shared bus adds a conversion function to the bus control unit that converts a logical address consisting of a unique name of the processor and a memory address into a physical address of the shared memory. It is characterized by the addition of a table.

〔Example〕

The compound computer system of the present invention will be explained below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the compound computer system of the present invention. Multiple processors (Pr~Pn
) and shared memory (CM) are each connected in parallel to a common bus (CB) to which a bus control unit (BC) is attached. The timing of using the memory of the processor is performed asynchronously.The processor transfers a bus use request signal to the bus control unit BC, receives a bus use permission signal from the bus control unit BC, and transfers the memory of each processor to the common bus CB. The common memory CM is accessed at the access timing.

In this way, the bus control unit BC gives the processor the right to use the common bus CB for each memory access of each processor, and at the same time stores the unique name and address of the processor output from the processor in the shared memory. 90M
It has an address conversion function to convert to the above address.

FIG. 2 is a block diagram showing an example of the configuration of the bus control section BC. The bus control unit BC decodes shared memory access commands from each processor flowing on the common bus CB, and provides a bus arbiter BA and a processor-specific unit that decodes the shared memory access command from each processor flowing on the common bus CB and gives the right to use the common bus CB to the processor that outputs the memory access command first. The name PN and the memory address output from the processor, the so-called logical address LA, are shared in the memo 90.
It is composed of an address conversion table AT that converts addresses on M, so-called physical addresses PA.

FIG. 3 is a diagram showing the concept of an address translation table.

The address of the shared memory CM is composed of a physical address PA, a processor name PN, and a memory address (logical address) LA output from the processor.

Next, the operation according to the present invention will be explained with reference to FIGS. 1 and 2. To simplify the explanation, two processors P,
, P2 use the shared memory CM. The input/output commands to the shared memory CM of the processor P1 are IN, 0UT1, and the input/output commands to the shared memory of the processor P2 are IN2, OUT2. An example will now be described in which the processor P1 outputs address 0001 and an OUT command to the shared memory CM. First, the processor 1 transmits a bus request signal to the bus control unit BC in order to obtain the right to use the common bus CB.

The bus request signal is generated using a specific OUT command set in advance. When the common bus CB use permission signal is returned from the bus arbiter BA of the bus control unit BC, the processor P1 writes the unique name PNI of the processor P1 on the common bus CB.
, address 0001° OUT command and data are output. In the bus control unit BC, the unique name PN of the processor P1
I and address 0001 are set in address converter AT, and converted to physical address 10001 on shared memory CM. Data is written to address 10001 on the shared memory CM using the converted physical address 10001 and the OUT command.

Next, an example will be described in which the processor P2 outputs an OUT command at address 0001 to the common memory CM in the same way as the processor P1. In order to acquire the right to use the common bus CB, the processor 2 transmits a bus request signal to the bus control unit BC, and obtains permission to use the common bus CB as described above. Processor P2 then writes processor 2's unique name PN2. on the common bus CB. Address 0001. Outputs OUT command and data. The bus control unit BC sets the processor-specific name PN2 and address 0001 in the address translation table AT, and changes it to the physical address 20001 on the shared memory CM.

Data is written to address 20001 on the shared memory CM using the converted physical address 20001 and the OUT command. In this way, the same logical address of processor P1 and processor P2 is expanded to each separate address on shared memory CM.

Next, an example will be shown in which the processor P1 executes an IN command for the logical address 0001 in the common memory CM.

As described above, first, permission to use the common bus CB is obtained from the bus control unit BC, and then the unique name PNI of the processor Pl, the logical address No. 0001, and the logical address No. 0001 and IN are written on the common bus CB.
Output instructions. Address converter AT of bus control unit BC
Now, the processor-specific name PNI and logical address 00.
01 to the physical address 10001, and data is input from address 10001 on the common memory CM.

The operation of the memory sharing device using two processors Pl and P2 has been described above, but the same applies to N processors.

〔Effect of the invention〕

As explained above, the compound computer system of the present invention is constructed from simple hardware, making full use of the effectiveness of the common bus coupling method, and is extremely effective in practical use.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a compound computer system according to the present invention, FIG. 2 is a block diagram showing an example of a bus control section forming a part of the present invention, and FIG. 3 is a block diagram showing an example of a bus control section constituting a part of the present invention. FIG. 2 is an explanatory diagram of an address translation table included in the . In the figure, P1 to Pfi are processors, CM is a shared memory, BC is a bus control unit, CB is a common bus, BA is a bus arbiter, AT is an address converter, PN is a processor name, LA is a logical address, and PA is a physical address. It is an address.

Claims (1)

[Claims] A plurality of processors and a shared memory that can be accessed by the processors are each connected in parallel via a common bus, and the common bus is connected to the processor when the processor accesses the address space of the shared memory of the processor. In a compound computer system, a bus control unit is added that gives the right to use a shared bus, and a conversion table is added to the bus control unit to convert a logical address consisting of a unique name of the processor and a memory address into a physical address of the shared memory. A compound computer system characterized by the following.