JPS63201760A - Testing and setting system - Google Patents

Abstract

PURPOSE:To obtain a comparatively simple hardware which can use a conventional software as it is, and does not impose at all on an operating system, by utilizing sufficiently the effectiveness of a computer composite system by a common bus coupling system. CONSTITUTION:An IN1 instruction of a processor P1 sends a bus use request signal to a bus control part 40, receives a bus use permitting signal from the bus control part 40, the IN1 instruction is allowed to flow to a common bus 50, and a shared memory Rm receives the IN1 instruction and executes a prescribed processing. On the other hand, a trapping device 30 traps the IN1 instruction flowing on the common bus 50, sets a storing circuit 32 in the trapping device 30, and sends a bus holding signal to the bus control part 40 through a bus holding line 60. Accordingly, the processor P1 holds continuously the right of using of the common bus 50, even if the IN1 instruction of the processor P1 is ended, and subsequently, an OUT1 instruction of the processor P1 is executed. Especially, as for a computer composite system, an attention must be paid to a protection of resources, but this means can realize it by a comparatively simple hardware.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a test and set method in a computer complex system using a common bus coupling method.

[Conventional technology]

In recent years, research has been conducted in various places to develop computer systems with excellent cost performance by combining multiple computers.
The results are highly anticipated.

In computer complex/systems, important issues include not only the connection form between computers and task scheduling, but also how to effectively use memory, input/output devices, files, etc. The advantages of a computer complex system using a common bus are that the cost of attached hardware is relatively low and the system is highly expandable. In particular, the shared memory method in multiprocessor systems is extremely effective in solving synchronization problems between processors, exclusion problems, data sharing, and improving the processing power and reliability of the entire system.

A problem here arises when multiple processors use one shared memory at the same time, that is, when one processor's task competes with another processor's task to access one shared memory. In this case, some tasks have a character that must be executed continuously, and a test-and-set function is required to prevent resources from being taken over by the unpacking task being executed.

[Problems to be solved by the present invention]

Conventionally, a common method of this type has been to prepare a common table for a plurality of processors on a common bus and manage resources using software for each processor or an operating system that manages the entire system.

In other words, when a processor monopolizes shared memory for a period of time (test-and-set operation), or when an operator receives a processor input/output instruction, the resource is A flag specific to the processor is set at the address of the table corresponding to This is a method of prohibiting the use of resources. This method has the disadvantage that it places a burden on the software and operating system of each processor, reducing the throughput of the entire system.At the same time, it requires a table for monitoring resource usage and a control unit for controlling the table. This has the extremely unreasonable drawback of increasing hardware costs.

[Means to solve the problem]

The present invention was developed in view of the various drawbacks mentioned above, and takes full advantage of the effectiveness of computer complex systems based on the common bus coupling method, and provides relatively simple hardware that allows conventional software to be used as is and does not place any burden on the operating system. This provides a test and set device that can be realized using

〔Example〕

The details of the test and set device of the present invention will be explained below with reference to the drawings. FIG. 1 shows the configuration of this test and set device. A plurality of processors (p1 to pn), a shared memory (Rm), and a trap device 30 are each connected in parallel to a common bus 50 to which a bus control section 40 is added. Further, the trap device 30 and the bus control unit 40 are connected to the bus holding line 6.
They are connected by 0. The timing of using the processor's resources is performed asynchronously, and the processor transfers a bus use request signal from the processor to the bus control unit 40, receives a bus use permission signal from the bus control unit 40, and transfers each bus to the common bus 50. It outputs various signals at the input/output timing of the processor. In this way, the bus control unit 40 sends the processors to the common bus 5 for each output command of each processor.
It has a function of granting the right to use 0 and at the same time allowing the common bus 50 to continue to be used by a bus hold signal from the trap device 30, which will be described later.

=5- FIG. 2 shows the configuration of the trap device 30.

The trap device 30 traps the shared memory input/output command flowing on the common bus 50, sets the memory circuit 32 in the trap device 30, and sends a bus hold signal to the bus control unit 40 via the bus hold line 60. Further, the trap device 30 traps the second input/output command to the shared memory flowing on the common bus 50, resets the memory circuit 32, and stops the holding signal sent to the bus control unit 40. The command interpretation circuit 31 in the device 30 is connected to the common bus 5.
This is a decoder that detects a test and set request instruction and a test and set release instruction among the input/output instructions flowing on 0.

The memory circuit 32 is constituted by an R-8 flip-flop circuit, etc., and is set by a test and set request instruction decoded by the instruction interpretation circuit 31 and reset by a test and set cancellation instruction also decoded by the instruction interpretation circuit 31.

Next, the operation of the test and set apparatus according to the present invention will be explained with reference to FIGS. 1 and 2. To simplify the explanation, an example will be described in which two processors Pl and P2 compete to use the shared memory Rm. INI, 0UT input/output instructions to shared memory of processor PI
I, and an input/output instruction I to the shared memory of processor P2
Assuming that N2.0UT2, each IN and OUT command must be used consecutively. In other words, IN
The command is a test and set request command, and the OUT command is a test and set release command. Therefore, the instruction interpretation circuit 31 in the trap device 30 must be configured to decode each IN command and OUT command into a predetermined command. Now let's say that the IN1 instruction is executed from processor Pl to processor P2 earlier than processor P2.
The INI command No. 1 sends all bus use request signals to the bus control unit 40. The bus control unit 40 receives a bus use permission signal, and the IN1 command is sent to the common bus 50. The shared memory Rm is
It receives an I command and executes a predetermined process. On the other hand, the trap device 30 traps the INI command flowing on the common bus 50, sets the memory circuit 32 in the trap device 30, and sends a bus hold signal to the bus control unit 40 via the bus hold line 60.

Therefore, the processor P1 continues to hold the right to use the common bus 50 even after the INI instruction of the processor P1 ends, and the 0UT1 instruction of the processor P1 continues to be executed.

The trap device 30 traps the 0UTl instruction of the processor P1 flowing on the common bus 50.
The memory circuit 32 in the memory is reset.

When the memory circuit 32 is reset, the bus hold signal sent to the bus control unit 40 is stopped and the 0U of the processor pl is
At the same time as the TI instruction ends, the right to use the common bus 50 held by the processor P1 is released. Therefore, during test and set processing of processor P1, processor P2
processing is not executed.

In the above explanation, only one resource and one test and set instruction were used, but the same applies to multiple resources and multiple test and set instructions.

That is, the instruction interpretation circuit 31 in the trap device 30 may be provided with a function of interpreting a plurality of test and set request commands and test and set cancellation commands of a plurality of processors.

In this way, by simply setting the test and set request instruction and the test and set release instruction in the input/output instructions to the processor's shared memory in advance, certain processing can be performed continuously without resources being taken over by other processors. Ru.

Particularly in computer complex systems, it is necessary to pay attention to resource security, but this method can be realized with relatively simple hardware by using the test-and-set method.

Furthermore, if there are many instructions registered as test and set instructions in the instruction interpretation circuit 31 in the trap device 30, it is conceivable to add a memory or a dedicated processor to perform the series of processes. Furthermore, a means for prohibiting all processors from using the common bus 50 when erroneous data or instructions flow on the common bus 50 can be easily added.

-1e- [Effects of the Invention] As explained above, the present test and set device is a test and set method that takes full advantage of the effectiveness of the common bus coupling method, and is extremely effective in practical use.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a test and set device according to the present invention, and FIG. 2 is a block diagram of a trap device forming a part of the present invention.

Claims (1)

[Claims] A plurality of processors and a shared memory that can be accessed by the processors are each connected in parallel to a common bus, and the common bus is connected to the common bus for each memory access of the processor to the address space of the shared memory. In a computer complex system to which a bus control unit is added that grants usage rights to the processor, a memory access to the common memory among the memory accesses of the processor on the common bus is trapped and transmitted to the bus control unit, and the processor continues to have the right to use the common bus, traps the processor's second access command to the common memory, transmits it to the bus control unit, and causes the processor to stop using the common bus. A test and set device characterized in that a trap device is connected.