JPH03225522A - Floating point arithmetic unit - Google Patents

Abstract

PURPOSE:To decrease the number of incrementer circuits and to realize high integration by using one incrementer circuit for both a rounding process and an absolute value generating process in common. CONSTITUTION:When the exponent parts Ex and Ey of input data X and Y are so set that Ex>Ey or Ex = Ey and the arithmetic result of an arithmetic circuit 32 is plus, a critical path is in the order of the circuit 32, a selector 34, a multi-bit left shifter 35, a selector 37, the incremeter circuit 38, a 1-bit right shifter 40, and a selector 39. When Ex = Ey and the arithmetic circuit of the circuit 32 is minus, on the other hand, the path is in the order of the circuit 32, an inverter circuit 36, the selector 34, the multi-bit left shifter 35, and the selector 39. The circuit 38 which performs both the rounding process and absolute value generating process need not perform the rounding process when Ex - Ey =0 and it is not necessary to perform the rounding process and absolute value generating process, so the circuit 38 can be used in common for both the rounding process and absolute value generating process. Consequent ly, one incrementer circuit can be omitted and the high integration becomes possible.

Description

[Detailed Description of the Invention] [Summary] Regarding a floating point arithmetic unit that adds and subtracts numbers in floating point notation, one incrementer circuit can be shared for rounding processing and absolute value processing, and the number of incrementer circuits can be reduced. The purpose is to provide a floating-point arithmetic unit that is suitable for integration and has a digit-alignment circuit that aligns the mantissas of two numbers in floating-point format, and adds or subtracts the digit-aligned mantissas. a signal generation circuit that generates a first instruction signal when the operation result of the addition and subtraction circuit is a positive value, and generates a second instruction signal when the operation result is a negative value;
a first selection circuit that can take either a first selection state that selects the output of the addition/subtraction circuit or a second selection state that selects the output of the second processing circuit; and a first selection circuit that normalizes the output of the first selection circuit. a processing circuit, an inversion circuit that inverts the polarity of the output of the addition/subtraction circuit, and a second selection that can take either a first selection state that selects the output of the first processing circuit or a second selection state that selects the output of the inversion circuit. a second processing circuit that rounds or converts the output of the second selection circuit into an absolute value; and a first selection state that selects the output of the second processing circuit or a second selection state that selects the output of the first processing circuit. and a third selection circuit capable of taking any of the following, each selection circuit taking the first selection state in response to the first instruction signal and taking the second selection state in response to the second instruction signal. Constructed as a characteristic.

[Industrial Application Field] The present invention relates to a floating point arithmetic device, and particularly to a floating point arithmetic device that adds and subtracts numbers in floating point notation.

In recent years, F P
U (floating point processes
Demand for floating point arithmetic units (sing u-nits) is increasing.

The FPU performs the necessary arithmetic processing on numbers in floating point notation to obtain the answer, and has features such as a wider dynamic range and higher precision than fixed point arithmetic.

[Conventional technology]

For example, when adding or subtracting numbers in floating point notation, the processing flow (however, the processing flow for the mantissa part) is shown in Figure 3. In step S1, the digits of the mantissa parts of input data After converting to the format and performing addition or subtraction in step S2, sequentially in steps S3 to 35,
Output data Z is obtained by appropriately performing absolute value processing, normalization processing, and rounding processing.

That is, the sign, exponent, and mantissa of the two numbers (X) and (Y) are respectively (SX, EX).

F, ), (sy, EY, FY), in addition and subtraction, first compare the exponents E and EY, align the exponent of the small value with the exponent of the large value, and set the mantissa of the number with the small exponent,
Shift to the right by the difference in exponents.

Next, add or subtract the mantissas considering the sign,
The result is normalized and the index is reduced by the shift fi required for normalization. At this time, if the exponent underflows, the answer Z is set to zero or Z is set to be a non-normalized number. (
When the result of addition/subtraction overflows, the mantissa is normalized and the exponent is increased. If the exponent overflows at this time, it is flagged as unoperable. In this way, Sz, Ez, and Fz can be determined.

Here, the input data X and Y are, for example, IEEE E
(Institute of Electrical
and Electronics Engineers
) expressed in floating point notation of the data format. IEE
There are two types of E data formats: single precision (32 bits) and double precision (64 bits).Double precision has a 1-bit sign part (
S), an exponent part (E) of 11 bits, and a mantissa part (F) of 52 bits, and S, E, and F represent the number of the following formula (2).

(-1)' 2E-bi” (1,F)・・・・・・■
However, below bias-1023, two numbers in floating point format used in this specification (
X, Y) shall be expressed by the following formulas (1) and (2).

X== (l) 5X2Ex-baas (l,
)' x ) ,,---■Y= (-1)"2
°ゞ−”S (1, Fy)・・・・・・■ FIG. 4 is a block diagram of a conventional example that executes the process shown in FIG. It can be divided into

The exponent processing unit 20 includes a sign calculator 20a and an exponent comparator 20.
b, a shift amount controller 20c, an exponent operator 20d, and a first incrementer 20e, and a mantissa processing unit 21
are a first selector 21a, a second selector 21b, a multi-bit right shifter 21c, an adder/subtractor 21d, an inversion circuit 21e,
A second incrementer 21f, a third selector 21g, a shift amount detector 21h, a multi-bit left shifter 21i, a rounding controller 21j, a third incrementer 21, and a 1-bit right shifter 211 are provided.

In such a configuration, each process of the mantissa part, that is, (■) "digit matching process" is performed by comparing the exponent parts Ex and Ev of the input data X and Y in the exponent comparator 20b, and for example, Ex
>Ev, the first selector 21a selects FX, and
Select Fy with the second selector 21b, and shift amount controller 2
Based on the signal from 0c, the multi-bit right shifter 21c shifts F by (Ex Ey) digits to the right to match the digits with FX. F, and F7 with digits aligned are input to the adder/subtractor 21d, and addition or subtraction is performed taking into account the signs Sx and Sv. 21e, and a negative complement is taken by the second incrementer 21f. (■) "Normalization processing" is performed by the multi-bit left shifter 21i according to the signal from the shift amount detector 21h. It is also performed by the 1-bit right shifter 21ffi, and (■) "Rounding processing" is performed by the rounding controller 21j and the third incrementer 21k.

Therefore, the critical bus in FIG. 4 is as follows.

Index comparator 20b→ Shift amount controller 20c→ Multi-bit right shifter 21c→ Adder/subtractor 21d→ Inversion circuit 21e→ Second incrementer 21f→ 3rd selector 21g→ Shift amount detector 21h→ Multi-bit left shifter 211→ To the third incrementer 21 → 1 bit right shifter 21i! .

[Problem to be solved by the invention]

However, in such a conventional floating point arithmetic unit, a dedicated incrementer (second incrementer 21f and third incrementer 21k) is provided for each of "absolute value processing" and "rounding processing". Because of this structure, the area occupied by the incrementer circuit is the second largest after, for example, the adder/subtractor 21d, which leads to an increase in the circuit scale of the entire floating-point arithmetic unit and hinders integration, which is a problem that needs to be solved. .

[Purpose of the invention]

The present invention was made in view of these problems, and
The purpose of this invention is to enable a single incrementer circuit to be shared for rounding processing and absolute value processing, reduce the number of incrementer circuits, and provide a floating-point arithmetic unit suitable for integration.

[Means to solve the problem]

In order to achieve the above object, the present invention has two numbers (x, y,
), and an addition/subtraction circuit 11 that adds or subtracts the digit-adjusted mantissa part.
and a signal generating circuit 12 which generates a first instruction signal when the calculation result of the addition/subtraction circuit 11 is a positive value, and generates a second instruction signal when the calculation result is a negative value, and the output of the addition/subtraction circuit 11 are selected. a first selection circuit 13 that can take either a first selection state that selects the output of the second processing circuit 17 or a second selection state that selects the output of the second processing circuit 17;
The processing circuit 14, the inversion circuit 15 that inverts the polarity of the output of the addition/subtraction circuit 11, and either a first selection state in which the output of the first processing circuit 14 is selected or a second selection state in which the output of the inversion circuit 15 is selected. a second selection circuit 6 that can take the output of the second selection circuit 16, a second processing circuit 17 that rounds or converts the output of the second selection circuit 16 into an absolute value, and a first selection state or a second selection circuit that selects the output of the second processing circuit 17; a third selection circuit 18 that can take any of the second selection states for selecting the output of the first processing circuit 14;
Each of the selection circuits 13, 16 and 18 assumes a first selection state in response to a first instruction signal, and assumes a second selection state in response to a second instruction signal. .

[Effect]

In the present invention, the critical bus when the calculation result of the addition/subtraction circuit 11 is a positive value and the critical path when the calculation result is a negative value are as follows.

-Correct road■ place money- Addition/subtraction circuit 11 → first selection circuit 13 → first processing circuit 14 → second selection circuit 16 → second processing circuit 17 → third selection circuit 18, 11 ordinary l money- addition/subtraction circuit 11 → Inversion circuit 15 → Second selection circuit 16 → Second processing circuit 17 → First selection circuit 13 → First processing circuit 14 → Third selection circuit 18, where the second processing circuit 17 performs rounding processing and absolute value conversion. However, rounding processing is performed when the operation result is a negative value (
Although it is not necessary to perform rounding processing and absolute value processing at the same time when the difference between the exponents of data By combining the circuits into one, the circuit scale can be reduced.

〔Example] Hereinafter, the present invention will be explained based on the drawings.

FIG. 2 is a diagram showing an embodiment of a floating point arithmetic device according to the present invention, and is a diagram showing a main part corresponding to the mantissa processing section 21 in FIG. 4. For parts not shown in FIG. 2, refer to FIG. 4.

First, the configuration will be explained. In FIG. 2, numeral 30 represents a mantissa processing section, and the mantissa processing section 30 includes the following sections.

That is, a digit alignment circuit 31 includes a first selector 31a, a second selector 31b, and a multi-bit right shifter 31c, and aligns the digits of the mantissa parts (FX, FY) of two numbers (x, y) in floating point format. , an addition/subtraction circuit 32 that adds or subtracts the mantissa part whose digits have been aligned, and an addition '$i calculation circuit 3.
If the calculation result of step 2 is a positive value, the first instruction signal S is generated, while if the result is a negative value, the second instruction signal S is generated.
A first selection state (state P1) selects the signal generation circuit 33 that generates the instruction signal 3.4 and the output of the addition/subtraction circuit 32.
) or a second selection state (stay 1-Nl) that selects the output of the incrementer circuit 38, which will be described later, and normalizes the output of the third selector 34. A multi-bit left shifter 35 as a first processing circuit for processing, an inversion circuit 36 that bit-inverts the output of the addition/subtraction circuit 32, and a first selection state (state pz) or inversion circuit that selects the output of the multi-bit left shifter 35. 2nd selection state (stay) to select 36 outputs (Nz)
a fourth selector 37 as a second selection circuit that can take any of the following; and an incrementer circuit 3 as a second processing circuit that rounds or converts the output of the fourth selector 37 into an absolute value.
8, and a third selection state that can be either a first selection state (state P3) that selects the output of the third day of the incrementer circuit or a second selection state (state N3) that selects the output of the multi-bit left shifter 35. A fifth selector 39 as a circuit,
and configure it.

However, the third to fifth selectors 34, 37, and 39 assume the first selection state (states p, , p2, and P3) in response to the first instruction signal (S,), while SN
) in response to the second selected state (states N+, Nz,
N3).

Note that 40 is a 1-bit right shifter, 41 is a shift amount detector, and 42 is a rounding controller.

Next, the effect will be explained.

First, the input data X,
The exponent parts Ex and Ev of Y are compared, and if, for example, EX>EY, the first selector 31a selects the mantissa part F of data X, and the second selector 31b selects the mantissa part FY of data Y, Based on the signal from the shift amount controller 20c (see FIG. 4), the multi-bit right shifter 31c shifts Fy to (
EX-E, ) digits are shifted to the right and the digits are aligned with Fx.

Next, Fv and Fx whose digits have been matched are input to the adder/subtractor 21d, and addition or subtraction is executed taking into account the codes SX and SY. At this time, a predetermined instruction signal is output from the signal generation circuit 33 according to the calculation result of the addition/subtraction circuit 32. Here, considering the case of Ex≠Ey, in the case of subtraction, the small temporary GFv is always subtracted from the large mantissa, that is, FX in this case, so the calculation result of the adder/subtractor 21d is always a positive value, so the instruction signal becomes the first instruction signal SP. This results in
The third selector 34, the fourth selector 37, and the fifth selector 39 are all in the first selection state (stay) P, , P, ,
P3), and the critical path at this time is as follows: addition/subtraction circuit 32 → third selector 34 → multi-bit left shifter 35 → fourth selector 37 → incrementer circuit 38 → 1-bit right shift 40 → fifth selector 39.

On the other hand, the input data χ,
As a result of comparing the exponent parts of Y, if Ex=Ey, the magnitude relationship of the mantissas cannot be determined, so the calculation result of the addition/subtraction circuit 32 may be a positive value or a negative value. Addition/subtraction circuit 32
If the calculation result is a negative value, the signal generation circuit 33 outputs the second instruction signal SN. As a result, the third selector 34, the fourth selector 37, and the fifth selector 39
All in the second selection state (states N+, Nz, N3
), and in this case, the paste:J logical path is as follows: Addition/subtraction circuit 32→Inversion circuit 36→Fourth selector 37→Incrementer circuit 33→Third selector 34→Multi-bit left shifter 35→Fifth selector 39.

Here, the incrementer circuit 38 as the second processing circuit
performs rounding and absolute value processing, but
Rounding processing does not need to be performed when Ex Ey-0, and rounding processing and absolute value processing do not need to be performed at the same time, so the incrementer circuit 38 can be shared by rounding processing and absolute value processing. , the number of incrementer circuits can be reduced by one compared to the conventional example.

In this embodiment, two new selectors (third selector 3
4 and a fifth selector 39) are added. However, usually
Since the area of one incrementer circuit is much larger than the area of two selectors, the area of the entire floating-point arithmetic unit can be significantly reduced, contributing to integration.

Furthermore, in this embodiment, by setting the fifth selector 39 to the second selection state (state N), the incrementer circuit 38 can be passed, which has the effect of improving the processing speed.

〔Effect of the invention〕

According to the present invention, it is possible to share one incrementer circuit for rounding processing and absolute value processing, reducing the number of incrementer circuits, and providing a floating point arithmetic device suitable for integration.

[Brief explanation of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention, and FIG. 2 is a diagram illustrating an embodiment of a floating-point arithmetic unit according to the present invention. Fig. 3.4 is a diagram showing a conventional example, Fig. 3 is a flow diagram of its addition/subtraction processing, and Fig. 4 is its configuration diagram. 10... Digit alignment circuit, 11... Addition/subtraction circuit, 12... Signal generation circuit, 13... First selection circuit, 14...・First processing circuit, 15... Inversion circuit, 16... Second selection circuit, 17... Second processing circuit, 18... Third selection circuit, 31... digit alignment circuit, 32... addition/subtraction circuit, 33... signal generation circuit, 34... third selector (first selection circuit) , 35
...Multi-bit left thick (first processing circuit) 36.
...Inverting circuit, 37...Fourth selector (second selection circuit), 38
...Incrementer circuit (second processing circuit) 39...Fifth selector (third selection circuit) Fig. Flowchart of conventional addition/subtraction processing Fig.

Claims (1)

[Claims] A digit alignment circuit (10) that aligns the digits of the mantissas of two floating-point numbers (X, Y), and an addition/subtraction circuit (11) that adds or subtracts the digit-aligned mantissas. , a signal generating circuit (12) that generates a first instruction signal when the calculation result of the addition/subtraction circuit (11) is a positive value, and generates a second instruction signal when the calculation result is a negative value; )
A first selection state or a second processing circuit (1
7); a first selection circuit (13) that can take any of the second selection states; a first processing circuit (14) that normalizes the output of the first selection circuit (13); An inverting circuit (1) that inverts the polarity of the output of the circuit (11).
5); and a second selection circuit (16) capable of taking either a first selection state in which the output of the first processing circuit (14) is selected or a second selection state in which the output of the inversion circuit (15) is selected; a second processing circuit (17) that rounds or converts the output of the second selection circuit (16) into an absolute value;
A first selection state or a first processing circuit (1
and a third selection circuit (18) capable of taking either of the second selection states for selecting the output of 4), each of the selection circuits (13, 16, 18) responding to the first instruction signal. A floating point arithmetic device characterized in that it takes a first selection state and takes a second selection state in response to a second instruction signal.