JPH03225822A - Manufacture of wiring - Google Patents

Abstract

PURPOSE:To make it possible to form a wiring for a semiconductor device which is highly electromigration-proof and has a long life by forming extensively a conductor film for wiring which includes at least Al and thereafter, performing a heat treatment before patterning it after a predetermined wiring shape. CONSTITUTION:After forming an insulating film 20 on a semiconductor substrate 10, a P-type or an N-type doping region 11 of high concentration is formed by an implantation of ions performed selectively through a predetermined mask and by a heat treatment performed subsequently. After removing the thin oxide film formed on the surface of the impurity doping region 11 by a water solution including hydrofluoric acid, a W film 40 is formed using a usual magnetron sputtering method. Successively, after forming an Al Si film 30, the W firm 41 is formed again thereon. After performing in this state the heat treatment in an atmosphere of hydrogen, a wiring is formed by working the W film 41 into a predetermined shape using an automatic etching. Thereby, the deterioration of the performance of the wiring caused due to the migration of the wiring including Al is suppressed, and the fine wiring of high reliability can be attained.

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a method for manufacturing wiring for semiconductor devices, and more specifically, a method for manufacturing wiring for semiconductor devices that has high electromigration resistance, has a long life, and is suitable for semiconductor devices having high integration density. Regarding the method. [Prior Art] As is well known, films of alloys containing AQ as a main component have generally been used as interconnects for semiconductor devices. However, as the degree of integration of semiconductor devices increases and wiring with even higher characteristics and reliability is required, single-layer A
Instead of M alloy film, for example, the 26th Annual Proceedings Reliability Physics (1988
26th Annual) pages 173 to 178 (26th Annual
ProceedingsRe1abilityP
hysics, (1988) PP, 173-1
78, H,)1. Hoang, “Effect
sof Annealing Temperature
on ElectromigrationPerfo
rmance of Multilayer Meta
llization systems,"), it has been proposed to use a laminated film formed by laminating a plurality of conductive films as wiring. [Problem to be solved by the invention] However, It has been found that wiring having a laminated structure has a small improvement in performance and is insufficient for future high current densities, especially in terms of electromigration.In other words, according to the inventor's study, wiring for semiconductor devices. The electromigration resistance of AQ film and A
It was found that the improvement strongly depends on the film quality of the 2-alloy film, and that simply forming a laminated structure does not improve the performance. In other words, when comparing wirings made from a single-layer AQSi film and a laminated film formed by overlapping an AQSi film on a W film through a current conduction test, it is found that when the line width is large, the lifespan of the laminated film wiring is longer than that of the single-layer film wiring. Although longer, as wiring becomes finer, the resistance of laminated film wiring increases rapidly when energized for a much shorter time than in the case of single-layer film wiring, as shown in Figure 2, for example. It has been found that by forming a laminated film, the lifespan is shortened on the contrary. Although the reason for the shortened lifespan due to such lamination is not clear, it is presumed that the layering actually deteriorates the film quality of the AQ film, thereby making it easier for electromigration to proceed. For example, in wiring created using a conventional method, the laminated structure had smaller crystal grain size and lower orientation. Moreover, it was found that the crystal grain size depends on the wiring width, and the narrower the width, the smaller the grain size. An object of the present invention is to provide a method for manufacturing wiring for a semiconductor device that solves the above-mentioned problems of conventional wiring and can form wiring for a semiconductor device that has high electromigration resistance and has a long life. . [Means for Solving the Problems] The above object is achieved by performing heat treatment after forming a conductor film for wiring containing at least aluminum over the entire surface and before patterning it into a predetermined wiring shape. The above object also includes a method of manufacturing a wiring using an aluminum silicon alloy as the conductive film, a method of manufacturing a wiring in which the conductive film is an aluminum-silicon alloy film,
A method for manufacturing a wiring, wherein the conductive film is a laminated film of a single layer of an aluminum silicon alloy film and a single layer of a high melting point conductive film, the high melting point conductive film is a high melting point metal, and an alloy containing the high melting point metal. or a method for manufacturing a wiring that is a film of a compound containing the high melting point metal, a method for manufacturing a wiring in which the high melting point metal is tungsten, molybdenum, titanium, or tantalum, and a single layer of the high melting point conductive film is formed by bias sputtering. The temperature of the heat treatment is 300 to 450°C. The above object further provides a method of manufacturing a wiring, wherein the conductive film is an alloy film containing at least aluminum and copper, a method of manufacturing a wiring, wherein the conductive film is a single layer of the alloy film, the conductive film is a single layer. A method for producing a wiring comprising a laminated film of the above alloy film and a single layer of a high melting point conductor film, wherein the high melting point conductor film contains a high melting point metal, an alloy containing the high melting point metal, or the high melting point metal. In the method for manufacturing wiring that is a compound film, the high melting point metal is tungsten,
Molybde method. 6. A method for manufacturing a wiring in which the high melting point metal is tantalum, a method for manufacturing a wiring in which the single layer of the high melting point conductive film is formed by bias sputtering, and a manufacturing method for manufacturing a wiring in which the temperature of the heat treatment is 350 to 500°C. a semiconductor device including a wiring formed by the above manufacturing method; a semiconductor device in which the wiring has particles having a particle size larger than the width of the wiring; This can be achieved by using a semiconductor device with a higher degree of orientation. [Function] When current is applied to a wiring made of a laminated film of an AQ alloy film and a film of different conductive materials such as W or jTa, a void region of AQ is generated in the AQ alloy film due to the movement of Afl. When the void grows and crosses the AQ alloy film, current flows through the different conductive material film, but the resistance value of the different conductive material film is A.
Since it is larger than the Q alloy film and has a higher current density, the temperature locally increases due to Joule heat generation. When the temperature rises above a certain limit, deterioration processes such as fusing and oxidation progress, leading to wire breakage. The movement of the AQ atoms occurs mainly through grain boundaries. Therefore, by aligning the crystal orientation, coarsening the crystal grains, and reducing the grain boundaries, the movement of the AQ atoms is suppressed, and the accompanying increase in resistance and disconnection are prevented, thereby extending the life of the wiring. realizable. In the present invention, after forming a conductor film for wiring over the entire surface, annealing is performed at a predetermined temperature, and then patterning is performed in a predetermined shape to enlarge the crystal grains. Conventionally, contrary to the present invention, annealing was performed after patterning into a predetermined shape, but with this method, the area of the side surface of the conductive film is relatively large compared to the contact area between the conductive film and the base. Therefore, the stress generated in the conductor film due to the difference in thermal expansion coefficient with the base is removed from the side surface, so the stress remaining in the conductor film is small, and as a result, the growth of the crystal grains is suppressed. The particles become fine and electromigration is more likely to occur. On the other hand, in the present invention, since annealing is performed with the conductive film formed on the entire surface, the contact area between the conductive film and the base is extremely large, and the area of the ventral surface relative to this can be ignored. Therefore, the stress generated within the conductor film is
The crystal grains remain within the film without being removed to the outside, and as a result, the crystal grains grow significantly and become coarse, thereby effectively suppressing the movement of AQ atoms and the occurrence of electromigration. In this way, the present invention reverses the order of annealing and patterning to enlarge crystal grains and improve A
Since it suppresses the movement of M atoms, AQ film and AQ
Needless to say, the present invention can be used both when wiring is formed using a single layer of an alloy film and when wiring is formed by laminating another conductive film with an AQ film or an AQ alloy film. In the conventional case, the occurrence of the above-mentioned failure was particularly severe when the width of the wiring became small, but in the present invention, although patterning is performed after annealing, the crystal grains are coarsened regardless of the width of the wiring. The present invention is particularly useful for forming interconnects in high-density semiconductor integrated circuits in which interconnect widths are extremely small. [Example] The present invention will be described below with reference to Examples. Embodiment 1 FIG. 1 is a sectional view showing an embodiment of the present invention. After an insulating film 20 was formed on the conductor film 10 on which the active portion was formed by a normal semiconductor device manufacturing process, the wiring of the present invention was formed. Symbol 11 is a highly concentrated P type or N type formed by selective ion implantation using a predetermined mask and subsequent heat treatment.
The wiring, which indicates the type doped region, is the A2 film 30 and the W film 40, 4.
Consists of 1. After removing the thin oxide film formed on the surface of the impurity doped region 11 with an aqueous solution containing hydrofluoric acid,
Film thickness: 1100n using normal magnetron sputtering method
A W film 4o of 500 nm in thickness was formed, and then an Al2
After forming the Si film 30, a W film 41 with a thickness of 50 nm was again formed thereon. In this state, heat treatment was performed in a hydrogen atmosphere at a temperature of 250 to 500° C. for 9 hours and 30 minutes, and then processed into a predetermined shape using a well-known auto-etching technique to form wiring. As well as traditional manufacturing process for comparison. After processing the laminated film into the shape of a wiring, a heat treatment was performed under the above conditions to create a wiring. The relationship between the heat treatment temperature and crystal grain size in these wirings is shown in FIG. In those processed into the shape of wiring after heat treatment, the crystal grain size of 80 was independent of the wiring width and grew into large particles, as shown in FIG. 3(a). Line width is 0.
Even with 8 μm wiring, A
The Q grain size is 1.0 μm or more, and a wiring having a so-called bamboo structure in which the crystal grains grow larger than the wiring width is realized. On the other hand, the one processed into a wiring shape according to the conventional method and then subjected to heat treatment is shown in Fig. 3(b).
As shown in , the grain size of AM depends on the wiring width, and when the wiring width was 6 μm or more, a grain size of 1 μm or more was obtained, but the narrower the wiring width, the smaller the crystal grains, and the wiring Width is 0
．． In the case of 8 μm, even if the heat treatment temperature was 600° C., the particle size was only about 0.5 μm. That is, in the laminated wiring with a small wiring width formed by the conventional method, the grain size of AQ was smaller than the wiring width, and it was recognized that the Aff film did not form a perfect bamboo structure. The crystal grain size of the AQ wiring was measured after the device was completed, and
Regarding the crystal grains of the wiring having a bamboo structure, the distance between adjacent bamboos was defined as the grain size. The width of these wirings was changed and current was applied to measure the equivalent wiring life (unit: Ms: 10' seconds) of each wiring, and the electromigration resistance was compared. The results obtained are shown in Table 1. 1st table wiring structure: W/AQSi/W (501500/10
0 nm thickness) Unit: Ms (10' seconds) As is clear from Table 1, when the above laminated film is processed into a wiring shape and then heat-treated, the wiring becomes finer as the wiring becomes finer. The lifespan decreased, and the decrease in the lifespan was particularly significant for wirings with a width of 1.0 μm or less. However, when wiring is formed according to the present invention in which heat treatment is performed before the above-mentioned processing, even if the wiring becomes finer and has a diameter of 1.0 μm or less,
No decrease in lifespan was observed, and it was confirmed that a fairly constant lifespan could be maintained. Furthermore, the W film on the AffiSi film was formed at a temperature below 200°C, at which the AQ crystal grains hardly grow.
It has been found that by subjecting the wire to the process of the present invention, the life span of the wire can be further improved by several tens of percent to several times. In addition, in this example, a high melting point metal film was provided under the Al film, but similar remarkable effects were observed in wiring having a structure that does not have this high melting point metal film. In this example, the heat treatment was performed using a normal furnace, but an infrared lamp irradiation type heating device was used to perform the heat treatment at a high temperature. It goes without saying that a similar effect can be obtained even if heat treatment is performed for a short time. Embodiment 2 FIG. 4 is a sectional view of a semiconductor device showing another embodiment of the present invention. After forming the insulating film 20 on the conductor film 10 on which the active portion has been formed by a normal semiconductor device manufacturing process, the wiring of the present invention is formed. Symbol 11 indicates a region doped with a highly concentrated P-type or N-type impurity, which is formed by ion implantation selectively performed using a predetermined mask and subsequent heat treatment. The wiring consists of an A11 film 30 and W films 40 and 41. The thin oxide film formed on the surface of the impurity-doped region 11 was removed using an aqueous solution containing hydrofluoric acid. Using a normal magnetron sputtering method, a W film with a thickness of 1100 nm was formed without applying a bias to the substrate.
A film 40 was formed, and a bias of about 100 V was applied to the surface thereof to form a W film 61 with a thickness of about 20 nm. Subsequently, after forming an AQSi film 30 with a thickness of 500 nm, a W film 41 with a thickness of 50 nm was formed again without applying a substrate bias. It was processed into a predetermined shape using ordinary photoetching technology and used as the first layer of wiring. The laminated film was processed and heat treated using the conventional method and the method shown in Example 1, that is, the method in which heat treatment is performed before processing into a wiring shape, and the performance of the two types of samples obtained was compared. When we examine the orientation of W using X-ray diffraction, we find that there is almost no orientation in the lowermost W film 40 formed by normal sputtering (measured using a normal diffractometer).
110) Although the diffraction peak shows the maximum intensity, it does not become a clear peak in so-called rocking curve measurement), but it is strong in the W film layer 61 formed by bias sputtering (
110) Orientation is observed and the half width of the rocking curve is approximately 1
0 degrees, and a clear peak was observed (see Figure 5)
. For comparison, when comparing the AQSi film 30 film type 0 degree using rocking curves, the above W film 61 is compared with the AQSi film 30 film type 0 degree.
When film type 0 is provided, the W film 61 is more similar to the W film 40 and AQ.
It was found that the degree of (11,1) orientation (peak intensity value) was several times to several tens of times stronger than in the case where the Si film 30 film type 0 was not present (see FIG. 6). The patterned wiring was subjected to hydrogen annealing at 450"C for 30 minutes, and then subjected to S
It was covered with an iO2 insulating film 21, and an opening was provided at a predetermined position. A selective CVD method using tungsten hexafluoride as a source gas is applied only to the opening to form a film with approximately the same thickness as the insulating film 21.
A W plug 43 with a thickness of 0.00 nm was formed. Similarly to the first layer wiring, a W film 42 with a thickness of 1100 nm is formed, and a W film 62 with a thickness of approximately 20 nm is formed by sputtering with a bias of approximately 100 V applied. Subsequently, a three-layer film consisting of the AQ film 31 having a film thickness of 500 nm was formed, and after being heat treated in the same manner as above, it was processed into a predetermined shape to form a second layer wiring. Finally, this was covered with a SiO□ insulating film 22 formed by plasma CVD, and an opening was provided at the connection position with the outside. In this embodiment, the W films 40, 4
．． 1, 42, 61°62 were formed by sputtering method, but C
It may also be formed by the VD method. However, the orientation of the film is determined by CVD.
Since a film formed using the above method is not strong, it is preferable to form the W films 61 and 62 by bias sputtering. Table 2 shows the reliability evaluation results of the wiring portion of the element thus formed. The table shows the life of the current test and the effective resistivity of the laminated wiring converted to a test temperature of 200°C. Here, the life of the laminated wiring is 110% of the initial value of the wiring resistance.
took the time to reach. Table 2 Wiring structure: W/A Q Si /W (50/5
00/100nm thickness) effective resistivity ~4μΩ], unit: Ms (10r'' seconds) Wiring structure: AQSi/W (500/1100nm thickness) effective resistivity ~3.5μΩ, unit: Ms (10''seconds) ) In the above embodiment, W/A Q S i /W, or A
Although we have explained the case of using Al2Si such as QSi/W, the same level of longevity effect can be obtained by using an AQ gold alloy in which other elements such as AQSiCu are added in a range of several percent or less instead of AflSi. was recognized. AQSiC
Table 3 shows the lifespan when u is used. Table Wiring structure: AQSi-0.5w%Cu/W (500
/1100n thickness) Unit: Ms (10' seconds) Furthermore, if the degree of orientation was high and the film 61 was a continuous film with a film thickness of about 10 nm or more, the effect remained the same. When the film thickness is about 10 nm or less, as shown in FIG. 7, the wiring life rapidly decreases and the above-mentioned effect becomes smaller. The barrier layer provided between the conductor film and the AQ alloy film is not limited to W, but can also be made of high melting point metals such as MO, Ti, and Ta, and their alloys, and compounds such as TiN. Exactly the same long-life effect was observed when using the same method. Table 4 shows the results obtained when Tie and TiN were used. Table Wiring structure: AQSi/TiW (500/1100n thickness) Unit: Ms (10' seconds) Wiring structure: AQSi/TiN (500
/ 1100n thickness) Unit: Ms (10' seconds) Regarding the bias applied to the substrate during bias sputtering, as shown in Figure 8, a range of 50-400V was extremely effective in improving the life of the wiring. . Furthermore, the peak half-width also became significantly smaller within the above range, indicating that strong orientation occurred. Embodiment 3 FIG. 9 is a sectional view showing another embodiment of the present invention, which is the same as FIG. 4 except for the highly oriented layers 63 and 64. After an insulating film 20 was formed on the conductor film 10 on which the active portion was formed by a normal semiconductor device manufacturing process, the wiring of the present invention was formed. Symbol 11 is a highly concentrated P type or N type formed by selective ion implantation using a predetermined mask and subsequent heat treatment.
This is a type impurity doped region. The wiring consists of an AQ film 30.63 and a W film 40.41. After removing the thin oxide film formed on the surface of the impurity doped region 11 with an aqueous solution containing hydrofluoric acid, the substrate is biased by ordinary magnetron sputtering. A 100 nm thick W film 40 was formed without applying any. Subsequently, an AQSi layer with a thickness of 500 nm was formed. The first layer 63 of about 20 nm was formed by applying a substrate bias of about 50 V, and the remaining layer 30 was formed without applying this substrate bias. A W film 41 having a thickness of 50 nm was again formed thereon without applying a substrate bias. It was processed into a desired shape using ordinary photoetching technology and used as the first layer of wiring. Two types of samples were prepared and their performances were compared: one was processed and heat treated using the conventional method, and the other was processed using the method shown in Example 1, that is, one that was heat treated before being processed into a wiring shape. When examining the orientation of AQ and W using X-ray diffraction, it was found that the W layer 40
Although almost no orientation is observed in the AQ layer 63 formed by bias sputtering and the AQ layer 30 thereon, there is a strong 1 orientation.
11 orientations were observed. For comparison, the film thickness was 500 nm without providing the highly oriented film 63.
Wiring was also fabricated by forming and patterning an AQSi film 30 and a W film 41 with a thickness of 50 nm. Al2Si film 30
Comparing the degree of orientation of AQ using the rocking curve as described above, it is found that when the high degree of orientation film 63 is not provided, the degree of orientation of AQ (111
) The peak intensity was a fraction of a fraction to several tenths of a second, and almost no clear orientation was observed in the rocking curve. The patterned wiring was subjected to hydrogen annealing at 450°C for 30 minutes, and then 5-inch
2 was covered with an insulating film 21, and an opening was provided at a predetermined position. A selective CVD method using tungsten hexafluoride as a source gas is applied to only the opening to create a thickness approximately the same as that of the insulating film 21 (
A W plug 43 with a thickness of about 500 nm) was formed. Similarly to the first layer wiring, a W film 42 with a thickness of 1100n is formed, and then a bias of about 50V is applied to form an Affi layer (64) with a thickness of about 20nm, and then an AQ film with a thickness of 500nm is formed.
A film 31 was formed to form a three-layer film, and processed into a predetermined shape to form a second layer wiring. Finally, this was covered with a SiO□ insulating film layer 22 formed by plasma CVD, and an opening was provided at a connection position with the outside. Both the four-layer film 40.63, 30.41 and the three-layer film 42, 64.31 were formed continuously here without breaking the vacuum of the sputtering apparatus. W film 40, 41
42 was formed by a sputtering method, but it may also be formed by a CVD method. Table 5 shows the reliability evaluation results of the wiring portion of the element thus formed. This table shows the test temperature 20
It shows the life of the current test and the effective resistivity of the laminated wiring converted to 0°C. Here, the life of the laminated wiring was defined as the time when the wiring resistance reached 110% of its initial value. Table 5 Wiring structure: W/A Q Si /W (50/5
00/100 nm thickness) Unit: Ms (10' seconds) W/A Q Si/W A instead of laminated film wiring
A similar longevity effect was obtained even in a system in which other elements such as Q Cu5i were added in a range of several percent or less. The highly oriented film 63 remained effective as long as the film thickness was about 10 nm or more and was continuous dust. The barrier layer is not limited to W, but may also include M OgTi,
Exactly the same long-life effect was observed when using high melting point metals such as Ta and their alloys, or compounds such as TiN. Substrate bias during bias sputtering is 5O-400v
A lifespan improvement effect was observed within the range of . As described above, in the present invention, after forming an AQ or AQ alloy film and before patterning it into a predetermined shape, heat treatment is performed to increase the grain size, thereby extending the life of the wiring. . The temperature of the above heat treatment is determined depending on the type of AQ alloy,
It may be the same whether it is a single layer film or a laminated film. For example, in the case of AQSi alloy film. 300-450℃, AQ-Cu or AQSiC
In the case of a u-alloy film, if the temperature is about 350 to 500°C, good results can be obtained in both cases.The present invention is effective when the wiring width is small, and is particularly effective when the wiring width is 0.5 μm or less. In this case, bamboo structures are easily formed and the results are much better than traditional methods. [Effects of the Invention] As described above, according to the present invention, it is possible to suppress deterioration of wiring performance due to migration of wiring containing 8Ω, and to realize highly reliable fine wiring. 3,

[Brief explanation of drawings]

1, 4, and 9 are cross-sectional views showing different embodiments of the present invention, FIG. 2 is a curve diagram for explaining problems with conventional wiring, FIG. 3, FIG. 5, FIG. 6, FIG. 7, and FIG. 8 are curve diagrams for explaining the present invention in detail, respectively. 10... Si substrate, 11... Impurity doped region, 2
0゜21.22...Insulation, 30,31.32...A
12 alloy wiring or AQ area 40, 41, 42.4
3.. W film, 48.. W plug, 61.62. Highly oriented film (W), 63.64... Highly oriented film (AQ-3iχ Fig. Whisper cycle f'5 (Hagi) r Kyotu Taku 4 Kutaku Gou Zutu

Claims (1)

[Claims] 1. A step of forming an insulating film having an opening on the main surface of a semiconductor substrate, a step of forming a conductor film containing at least aluminum over the entire surface, and a heat treatment to form the conductor film. After increasing the grain size of the film, removing a predetermined portion of the conductive film to form a wiring extending from the main surface of the semiconductor substrate exposed through the opening onto the insulating film. A method of manufacturing a wiring including at least 2. The method of manufacturing wiring according to claim 1, wherein the conductor film is an aluminum-silicon alloy film. 3. The method of manufacturing a wiring according to claim 2, wherein the conductor film is a single-layer aluminum silicon alloy film. 4. The method of manufacturing wiring according to claim 2, wherein the conductive film is a laminated film of at least one layer of the aluminum-silicon alloy film and at least one high melting point conductive film. 5. The method of manufacturing wiring according to claim 4, wherein the high melting point conductor film is a film of a high melting point metal, an alloy containing the high melting point metal, or a compound containing the high melting point metal. 6. The wiring manufacturing method according to claim 5, wherein the high melting point metal is tungsten, molybdenum, titanium, or tantalum. 7. The wiring manufacturing method according to claim 4, wherein at least one layer of the high melting point conductive film is formed by bias sputtering. 8. The wiring manufacturing method according to any one of claims 2 to 7, wherein the temperature of the heat treatment is 300 to 450°C. 9. The method of manufacturing wiring according to claim 1, wherein the conductor film is an alloy film containing at least aluminum and copper. 10. The method for manufacturing wiring according to claim 9, wherein the conductor film is a single layer of the alloy film. 11. Claim 9, wherein the conductive film is a laminated film of at least one layer of the alloy film and at least one high melting point conductive film.
Method of manufacturing the wiring described. 12. The method for manufacturing wiring according to claim 11, wherein the high melting point conductor film is a film of a high melting point metal, an alloy containing the high melting point metal, or a compound containing the high melting point metal. 13. The above-mentioned high melting point metals include tungsten, molybdenum,
13. The method for manufacturing a wiring according to claim 12, wherein titanium or tantalum is used. 14. At least one layer of the high melting point conductive film is biased.
Claims 11 to 13 formed by sputtering.
Method of manufacturing the wiring described. 15. The wiring manufacturing method according to claims 9 to 14, wherein the temperature of the heat treatment is 350 to 500°C. 16. A semiconductor device comprising wiring formed by the manufacturing method according to any one of claims 1 to 15. 17. The semiconductor device according to claim 16, wherein the wiring has particles having a particle size larger than the width of the wiring. 18. The semiconductor device according to claim 16 or 17, wherein at least one layer of the conductive film has a higher degree of orientation than the other films.