JPH0936113A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) [Abstract] [PROBLEMS] To provide a method for manufacturing a semiconductor device having a wiring having excellent wiring redundancy and excellent electromigration (EM) resistance and stress migration (SM) resistance. [Structure] Lower conductive layer 1 made of a tungsten (W) film
4 is ion-implanted with an inert gas species such as Ne, Ar, Kr, Xe or an impurity such as Si, and Al, C
The upper conductive layer 16 made of u, Ag, Au or an alloy layer based on them is laminated to form a laminated wiring. At least the crystal on the surface of the lower conductive layer formed of the W film or the like once formed is destroyed by ion implantation and changed to an amorphous structure. When an upper conductive layer of Al or the like is formed on the amorphous film by sputtering or the like, it is not affected by the orientation of the underlying crystal, and the upper conductive layer of Al or the like is aligned with the preferentially oriented plane.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a wiring of a semiconductor integrated circuit, and particularly to a wiring excellent in electromigration (EM) resistance and stress migration (SM) resistance. Regarding how to provide.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit, Al alloy wiring is generally used, but the wiring width has become less than 0.5 μm due to high density of elements. For this reason, higher reliability has been required in wiring. The following measures have been taken up to now for disconnection defects due to electromigration (EM) and stress migration (SM), which are problems in reliability of wiring.

As a first measure, Al is added by adding impurities.
There is a method of modifying the material itself. In this method, Al
On the other hand, Cu, Ti, Sc, etc. are added. As a second measure, there is a method of preventing an open defect (OPEN defect: disconnection, etc.) by utilizing a redundant effect by stacking Al wiring. For example, for Al wiring, TiN / Ti, T
i, TiW, W or the like is laminated.

As a third measure, there is a method of improving the Al crystallinity by improving the Al film forming method. For example, ICB
(Ion cluster beam) method for forming a single crystal Al film, or chemical vapor deposition (CVD) method for forming Al film
A method for forming a film can be exemplified.

Of these, the improvement of the reliability of the wiring by the stacking method which is the second measure is often used in combination with the impurity addition which is the first measure. Among the second measures, stacking with W is a point of improving reliability because W itself has the highest EM resistance among conductive materials and W has lower resistance than TiN or Ti. Considered to be effective.

[0006]

However, when the Al / W laminated film is formed by the usual sputtering method, the problem that the orientation of Al deteriorates occurs. Further, compared to the case where Al is formed on an amorphous structure film such as an oxide film,
There is a problem that the crystal grains of Al become small. That is, when an Al / W laminated film is formed by conventional normal sputtering, the orientation of Al is deteriorated and the grain size is small, so EM of Al is used.
Resistance will deteriorate. For this reason, when Al breaks, a high current concentrates on W in the lower layer, high Joule heat is generated, and the migration of Al is further accelerated, leading to defects.

As described above, in the laminated wiring of Al / W, W
Since the orientation of Al above deteriorates and the crystal grains become finer, the EM resistance of Al itself deteriorates. Therefore, there has been a demand for a method in which Al is (111) highly oriented on the W film and the grain size is increased. Further, for Cu, Ag wiring, etc., similarly to Al, a film with high orientation and large grain size is required.

The present invention has been made in view of the above circumstances, and provides a method of manufacturing a semiconductor device having wiring excellent in redundancy and excellent in electromigration (EM) resistance and stress migration (SM) resistance. The purpose is to do.

[0009]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises a step of ion-implanting impurities into the surface of a lower conductive layer, and a step of ion-implanting the impurities. Stacking an upper conductive layer on the surface of the conductive layer.

The lower conductive layer can be made of, for example, tungsten (W) or molybdenum (Mo), but is preferably made of W. This is because W has a high EM resistance by itself, and has a lower resistance than Ti or TiN.

Impurities implanted in the lower conductive layer are
It is preferable that the impurities are hard to react with the lower conductive layer.
For example, as the impurities, Ne, Ar, Kr, Xe
Inert gas species such as or Si and the like can be exemplified. By ion-implanting these impurities into the surface of the lower conductive layer, at least the surface becomes amorphous.

The upper conductive layer is made of Al, Cu, Ag, A
u or an alloy layer based on them is preferable. The lower conductive layer is preferably formed by a sputtering method or a chemical vapor deposition method.

The upper conductive layer is preferably formed by a sputtering method or a chemical vapor deposition method.

[0014]

In the method of manufacturing a semiconductor device having a laminated wiring using the ion implantation method of the present invention, at least the crystal on the surface of the lower conductive layer formed by the W film or the like is destroyed by the ion implantation, Change to an amorphous structure. When an upper conductive layer of Al or the like is formed on the amorphous film by sputtering or the like, it is not affected by the orientation of the underlying crystal, and the upper conductive layer of Al or the like is aligned with the preferentially oriented plane. For example, in an Al or Cu film having an fcc structure, the finest (111) orientation is achieved. Further, since it is not affected by the conformity with the underlying crystal lattice that suppresses the grain size growth of Al, the grains can grow large. Due to the above effects, the orientation of the upper conductive layer of Al, Cu, etc. is improved, the grain size of the crystal grains is increased, the number of grain boundaries is reduced, and it is difficult for atoms to move. Is improved.

Further, since the present invention basically has a laminated wiring structure, even if a disconnection or the like occurs in one conductive layer, conduction is supplemented by the other conductive layer, and a preferable redundant action is exhibited.

[0016]

EXAMPLES A method of manufacturing a semiconductor device according to the present invention will be specifically described below. In the process of manufacturing a semiconductor device, it may be desired to connect an impurity diffusion layer (or a lower wiring layer) formed on the surface of a semiconductor substrate and an upper wiring layer through a contact hole formed in an interlayer insulating film. . The present invention relates to a method of forming a wiring layer on the upper side thereof, and the wiring layer has a laminated structure. The details will be described below.

EXAMPLE 1 In this example, Ar is ion-implanted in a laminated wiring of Al-0.5% Cu and W. First, Figure 1
As shown in (A), a silicon substrate is prepared as the semiconductor substrate 2, a predetermined element is formed on the silicon substrate, and then a BPSG (boron and phosphorus-containing glass) film is formed to 700 nm as an interlayer insulating film 6. To do. Interlayer insulation film 6
Other than the BPSG film, a PSG (phosphorus-containing glass) film, a silicon oxide film, and a silicon nitride film can be used as the film.

Next, a contact hole 8 for exposing the surface of the impurity diffusion layer 4 on the surface of the substrate 2 is formed in the interlayer insulating film 6. Then, as shown in FIG. 1B, a Ti film 10 having a thickness of 30 nm and a T film are used as a base film and a barrier film.
The iN film 12 is formed with a film thickness of 70 nm in this order by a sputtering method. The sputtering conditions for the Ti film are as shown in Table 1 below.

[0019]

Table 1 Gas Ar = 100 sccm Pressure 0.4 Pa DC power 5 kW Substrate heating temperature 150 ° C. The sputtering conditions for the TiN film are as shown in Table 2 below.

[0020]

[Table 2] Gas Ar / N ₂ = 30/80 sccm Pressure 0.4Pa DC power 5kW Substrate heating temperature 150 ° C Then, as shown in FIG. 1C, a blanket tungsten (Blk-W) is used as the lower conductive layer 14. Is formed to have a thickness of 600 nm so as to enter the contact hole 8. Bl
The k-W film forming conditions are as shown in Table 3 below.

[0021]

Table 3 Gas WF ₆ / H ₂ / Ar = 75/500/2800 sccm Pressure 10640 Pa Film formation temperature 450 ° C. Here, W is used as a part of the wiring layer without etching bag. After forming the Blk-W film, Ar is implanted into the W film which is the lower conductive layer 14 by ion implantation, as shown in FIG. The implantation energy at this time is that the implantation energy is 6
The dose is 8 keV and the dose is 8 × 10 ¹⁵ / cm ² . The ion implantation conditions may be other conditions as long as at least the surface of the lower conductive layer 14 can be made amorphous.

Next, as shown in FIG. 2, the lower conductive layer 1
On the surface of No. 4, the upper conductive layer 1 made of Al-0.5% Cu
6 is formed by sputtering to obtain a laminated wiring layer.
The sputtering conditions for Al-0.5% Cu are as shown in Table 4 below.

[0023]

[Table 4] Gas Ar = 100 sccm Pressure 0.4 Pa DC power 5 kW Substrate heating temperature 150 ° C. After that, a wiring pattern is formed through a normal processing step.

In this embodiment, A as the upper conductive layer
As a result of investigating 1-0.5% Cu by XRD (X-ray diffraction), as shown in Table 5 below, the half-value width is 5 to 10 °, and it is well oriented to Al (111). It was confirmed. The grain size of Al-0.5% Cu was examined and found to be about 1 μm. The better the orientation and the larger the particle size, the better the EM resistance and SM resistance.

Further, in this embodiment, since the wiring layer has a laminated structure of the upper conductive layer 16 and the lower conductive layer 14, the redundancy is also good.

[0026]

[Table 5]

Comparative Example 1 A wiring layer having a laminated structure was formed in the same manner as in Example 1 except that ions were not implanted into the surface of the W film as the lower conductive layer 14. Similar to the first embodiment, the upper conductive layer 16
As a result of investigating Al-0.5% Cu as XRD by XRD (X-ray diffraction), as shown in Table 5 above, it is impossible to measure the full width at half maximum. It was confirmed to be inferior in comparison. Further, when the grain size of Al-0.5% Cu was examined, it was 0.3 μm or less, and it was confirmed that the grain size was also inferior to that of Example 1.

Comparative Example 2 A wiring layer having a laminated structure was formed in the same manner as in Example 1 except that a TiN film was used as the lower conductive layer 14 and the surface thereof was not ion-implanted. In the same manner as in Example 1,
Al-0.5% Cu as the upper conductive layer 16 is XRD
As a result of examination by (X-ray diffraction), as shown in Table 5, the full width at half maximum was 5 to 10 °, and it was confirmed that the Al (111) was well oriented. Also, Al-0.5
When the particle size of% Cu was examined, it was 0.5 μm or less,
It was confirmed that the particle size was inferior to that of Example 1. In addition, TiN is inferior to W of Example 1 in terms of conductivity.

Comparative Example 3 An Al-0.5% Cu film was formed on the silicon oxide (SiO ₂ ) film in the same manner as in Example 1. In the same manner as in Example 1, Al-0.5% C as the upper conductive layer 16 was used.
As a result of investigating u by XRD (X-ray diffraction),
As shown in (1), the full width at half maximum was 5 °, and it was confirmed that it was well oriented to Al (111). Al-
When the particle size of 0.5% Cu was examined, it was about 1 μm, and it is expected that the same EM resistance and SM resistance as in Example 1 can be obtained with Al-0.5% Cu alone.

However, the silicon oxide film is an insulating film or the like and is inferior in redundancy as compared with the first embodiment. Example 2 In this example, a laminated wiring of Al-0.5% Cu and W was formed in the same manner as in Example 1 except that Si was ion-implanted into the surface of the lower conductive layer 14. A wiring layer was formed. Descriptions of parts common to the first embodiment will be omitted, and only different points will be described.

In this embodiment, as shown in FIG.
After the lower conductive layer 14 made of Blk-W is formed under the same conditions as in the first embodiment, Si is implanted into the W film which is the lower conductive layer 14 by ion implantation, as shown in FIG. The implantation energy at this time is that the implantation energy is 60 ke.
V and dose amount is 8 × 10 ¹⁵ / cm ² . The ion implantation conditions may be other conditions as long as at least the surface of the lower conductive layer 14 can be made amorphous.

The subsequent steps are the same as in the first embodiment. In this example, Al-0.
As a result of investigating 5% Cu by XRD (X-ray diffraction), as shown in Table 5, the full width at half maximum is 5 to 10 ° and Al
It was confirmed that the orientation was good in (111). Moreover, when the particle size of Al-0.5% Cu was examined, it was 1 μm.
It was about. The better the orientation and the larger the particle size, the better the EM resistance and SM resistance. That is,
The laminated wiring according to this example is superior to the comparative examples 1 and 2 in EM resistance and SM resistance.

Further, in this embodiment, the wiring layer has a laminated structure of the upper conductive layer 16 and the lower conductive layer 14, so that the redundancy is better than that of Comparative Example 3. Example 3 In this example, a wiring layer having a laminated structure was formed in the same manner as in Example 1 except that Cu was used as the upper conductive layer 16. Descriptions of parts common to the first embodiment will be omitted, and only different points will be described.

In this embodiment, as shown in FIG.
After Ar was implanted into the W film which is the lower conductive layer 14 by ion implantation, Cu was deposited by the sputtering method to form the upper conductive layer 16a as shown in FIG. Cu
The sputtering conditions are as shown in Table 6 below.

[0035]

[Table 6] Gas Ar = 100 sccm Pressure 0.4 Pa DC power 8 kW Substrate heating temperature 300 ° C. Then, a wiring pattern is formed through a normal processing step.

In this embodiment, C as the upper conductive layer
As a result of investigating u by XRD (X-ray diffraction), it was confirmed that the orientation was good. Also, when the particle size of Cu was examined, it was about 1 μm. Orientation is good,
The larger the particle size, the better the EM resistance and SM resistance. That is, the laminated wiring according to this example is superior to the comparative examples 1 and 2 in EM resistance and SM resistance.

Further, in this embodiment, the wiring layer has a laminated structure of the upper conductive layer 16 and the lower conductive layer 14, so that the redundancy is better than in Comparative Example 3. Example 4 In this example, in a laminated wiring of Al-0.5% Cu and W, a laminated structure was formed in the same manner as in Example 1 except that Kr was ion-implanted into the surface of the lower conductive layer 14. A wiring layer was formed. Descriptions of parts common to the first embodiment will be omitted, and only different points will be described.

In this embodiment, as shown in FIG.
After forming the lower conductive layer 14 made of Blk-W under the same conditions as in the first embodiment, Kr is implanted into the W film which is the lower conductive layer 14 by ion implantation, as shown in FIG. The implantation energy at this time is that the implantation energy is 50 ke.
V and dose amount are 5 × 10 ¹⁵ / cm ² . The ion implantation conditions may be other conditions as long as at least the surface of the lower conductive layer 14 can be made amorphous.

The subsequent steps are the same as in the first embodiment. In this example, Al-0.
As a result of investigating 5% Cu by XRD (X-ray diffraction), as shown in Table 5, the full width at half maximum is 5 to 10 ° and Al
It was confirmed that the orientation was good in (111). Moreover, when the particle size of Al-0.5% Cu was examined, it was 1 μm.
It was about. The better the orientation and the larger the particle size, the better the EM resistance and SM resistance. That is,
The laminated wiring according to this example is superior to the comparative examples 1 and 2 in EM resistance and SM resistance.

Further, in this embodiment, the wiring layer has a laminated structure of the upper conductive layer 16 and the lower conductive layer 14, so that the redundancy is better than that of Comparative Example 3. Example 5 In this example, a wiring layer having a laminated structure was formed in the same manner as in Example 1 except that Ag was used as the upper conductive layer 16 and Xe was ion-implanted into the surface of the lower conductive layer 14. . Descriptions of parts common to the first embodiment will be omitted, and only different points will be described.

In this embodiment, as shown in FIG.
After forming the lower conductive layer 14 made of Blk-W under the same conditions as in the first embodiment, as shown in FIG. 1D, Xe is implanted into the W film, which is the lower conductive layer 14, by ion implantation. The implantation energy at this time is that the implantation energy is 50 ke.
V and dose amount is 8 × 10 ¹⁵ / cm ² . The ion implantation conditions may be other conditions as long as at least the surface of the lower conductive layer 14 can be made amorphous.

Next, as shown in FIG. 4, Ag was deposited by the sputtering method to deposit the upper conductive layer 16b.
The Ag sputtering conditions are as shown in Table 7 below.

[0043]

[Table 7] Gas Ar = 100 sccm Pressure 0.4 Pa DC power 10 kW Substrate heating temperature 350 ° C. After that, a wiring shape is formed through a normal processing step.

In this embodiment, A as the upper conductive layer
As a result of examining g by XRD (X-ray diffraction), it was confirmed that the g was well oriented. Further, when the particle size of Ag was examined, it was about 1 μm. Orientation is good,
The larger the particle size, the better the EM resistance and SM resistance. That is, the laminated wiring according to this example is superior to the comparative examples 1 and 2 in EM resistance and SM resistance.

Further, in this embodiment, the wiring layer has a laminated structure of the upper conductive layer 16 and the lower conductive layer 14, so that the redundancy is better than that of Comparative Example 3. In addition, the present invention
The present invention is not limited to the above examples, and various modifications can be made within the scope of the present invention.

[0046]

As described above, according to the method of manufacturing a semiconductor device of the present invention, the following effects can be obtained. 1. A is a highly conductive layer that substantially controls the wiring resistance.
The crystal orientation of the upper conductive layer composed of the l film, the Cu film, the Ag film, etc. is improved and the grain size is increased, and the EM resistance of the wiring layer composed of the wiring of the laminated structure is improved.

2. When W is used as the lower conductive layer, the reliability of the wiring as a whole is significantly higher than that of the conventional laminated structure wiring using TiN or the like due to the high EM resistance of W itself. 3. As the line width is reduced, the effect of improving the EM resistance is improved, and the effect is expected to be applied to high density devices in the future.

4. Since the present invention basically has a laminated wiring structure, even if a disconnection or the like occurs in one conductive layer, conduction is supplemented by the other conductive layer, and a preferable redundancy effect is achieved.

[Brief description of drawings]

1A to 1D are schematic cross-sectional views of a main part showing a manufacturing process of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a schematic sectional view of a key portion showing a step following that shown in FIG.

FIG. 3 is a schematic cross-sectional view of a main part showing a step following that shown in FIG. 1D according to another embodiment of the present invention.

FIG. 4 is a schematic view of another embodiment of the present invention, FIG.
FIG. 8 is a schematic sectional view of a key portion showing a step following that shown in FIG.

[Explanation of reference numerals] 2 ... Semiconductor substrate 4 ... Impurity diffusion layer 6 ... Interlayer insulating film 8 ... Contact hole 10 ... Ti film 12 ... TiN film 14 ... Lower conductive layer 16, 16a, 16b ... Upper conductive layer

Claims (8)

[Claims] 1. A method of manufacturing a semiconductor device having a laminated wiring composed of a lower conductive layer and an upper conductive layer, comprising a step of ion-implanting an impurity into a surface of the lower conductive layer, and the ion-implanting of the impurity. And a step of stacking an upper conductive layer on the surface of the lower conductive layer. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the lower conductive layer is made of tungsten. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the impurities implanted into the lower conductive layer are impurities that are difficult to react with the lower conductive layer. 4. The impurity is Ne, Ar, Kr, Xe.
The method for manufacturing a semiconductor device according to claim 3, wherein the inert gas species is Si or Si. 5. The upper conductive layer comprises Al, Cu, Ag,
It is Au or an alloy layer based on them,
5. The method of manufacturing a semiconductor device according to any one of 4. 6. The method for manufacturing a semiconductor device according to claim 1, wherein the lower conductive layer is formed by a sputtering method or a chemical vapor deposition method. 7. The method of manufacturing a semiconductor device according to claim 1, wherein the upper conductive layer is formed by a sputtering method or a chemical vapor deposition method. 8. The method of manufacturing a semiconductor device according to claim 1, wherein the crystalline state of at least the surface of the lower conductive layer becomes an amorphous structure by the ion implantation of the impurities.