JPH03225829A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH03225829A
JPH03225829A JP2106190A JP2106190A JPH03225829A JP H03225829 A JPH03225829 A JP H03225829A JP 2106190 A JP2106190 A JP 2106190A JP 2106190 A JP2106190 A JP 2106190A JP H03225829 A JPH03225829 A JP H03225829A
Authority
JP
Japan
Prior art keywords
wiring layer
semiconductor substrate
alloy wiring
substrate
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2106190A
Other languages
Japanese (ja)
Inventor
Ryuji Iwama
岩間 竜治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2106190A priority Critical patent/JPH03225829A/en
Publication of JPH03225829A publication Critical patent/JPH03225829A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To fill a cavity sealed by an alloy wiring layer with the layer and to improve economy and reliability by forming the layer on a semiconductor substrate and then heating it in a high pressure inert gas atmosphere. CONSTITUTION:An alloy wiring layer 2 is formed on a semiconductor substrate 1 having a step 1a, and the substrate 1 is heat treated in a high pressure gas atmosphere. The substrate 1 in which such an Al wiring layer 2 is formed is placed in a holder 5, conveyed into the processing chamber 4 of a processor, the chamber 4 is sealed, and argon gas is supplied from an argon gas cylinder 8 to the chamber 4 through a pressure regulator 9. A current is supplied to a heater 6 by using a temperature regulator 7 in this state to heat it, thereby heating the substrate 1. Thus, the layer 2 having an excellent step coverage can be formed to be completely filled in the contact hole 1a of the substrate 1.

Description

【発明の詳細な説明】 〔概 要〕 段差を有する半導体基板上に合金配線層を形成する方法
の改良に関し、 半導体基板のコンタクトホール内に合金配線層が完全に
充填された、ステップ・カバレンジの良好な合金配線層
を形成することが可能となる半導体装置の製造方法の提
供を目的とし、 段差を有する半導体基板上に合金配線層を形成する工程
と、前記半導体基板を高圧ガス雰囲気中において加熱処
理する工程とを含むよう構成する。
[Detailed Description of the Invention] [Summary] Regarding the improvement of the method of forming an alloy wiring layer on a semiconductor substrate having steps, the present invention relates to a step coverage method in which the contact hole of the semiconductor substrate is completely filled with the alloy wiring layer. The purpose of the present invention is to provide a method for manufacturing a semiconductor device that makes it possible to form a good alloy wiring layer. The method is configured to include a step of processing.

〔産業上の利用分野〕[Industrial application field]

本発明は、半導体装置の製造方法に係り、特に段差を有
する半導体基板上に合金配線層を形成する方法の改良に
関するものである。
The present invention relates to a method for manufacturing a semiconductor device, and particularly to an improvement in a method for forming an alloy wiring layer on a semiconductor substrate having steps.

近年の半導体装置の配線層は、アルミニウム或いはアル
ミニウム合金を材料として用い、スパッタ法により薄膜
として形成されているが、素子の微細化及び配線構造の
多層化に伴い、下地基板の段差の縦横比、即ちアスペク
ト比が大きくなってきており、良好な段差被覆性(以下
、ステップ・カバレッジと称する)を持つ配線層を形成
することが困難になっている。
In recent years, the wiring layers of semiconductor devices have been formed as thin films by sputtering using aluminum or aluminum alloy as a material. However, as elements become smaller and wiring structures become more multilayered, the aspect ratio of the steps of the underlying substrate, That is, the aspect ratio is increasing, making it difficult to form a wiring layer with good step coverage (hereinafter referred to as step coverage).

以上のような状況から、良好なステップ・カバレンジを
持つ配線層を形成することが可能な半導体装置の製造方
法が要望されている。
Under the above circumstances, there is a need for a method of manufacturing a semiconductor device that can form a wiring layer with good step coverage.

〔従来の技術〕[Conventional technology]

従来の半導体装置のM合金配線層の製造方法について第
4図により詳細に説明する。
A conventional method for manufacturing an M alloy wiring layer of a semiconductor device will be explained in detail with reference to FIG.

従来の半導体装置の製造方法においては第4図に示すよ
うに、コンタクトホール21aを形成した半導体基板2
1の表面に、スパッタ法によりM合金配線層22を形成
している。
In the conventional semiconductor device manufacturing method, as shown in FIG. 4, a semiconductor substrate 2 with a contact hole 21a formed therein is
An M alloy wiring layer 22 is formed on the surface of the substrate 1 by sputtering.

この場合、コンタクトホール21aのアスペクト比が大
きな場合には、図に示すようにコンタクトホール21a
の壁面にはM合金配線層22が形成され、内部には図示
するような空隙が生じてM合金配線層22を充填するこ
とができず、良好なステップ・カバレンジを持つ配線層
を形成することが困難である。
In this case, if the aspect ratio of the contact hole 21a is large, the contact hole 21a is
The M alloy wiring layer 22 is formed on the wall surface of the wall, and a void as shown in the figure is generated inside, making it impossible to fill the M alloy wiring layer 22, thereby forming a wiring layer with good step coverage. is difficult.

このためスバ7タ成膜中の半導体基板21の温度を、配
線層の材料の融点付近の高温にして成膜を行うことによ
り、被覆性及び平坦性の改善を図っている。
For this reason, the temperature of the semiconductor substrate 21 during film formation is set to a high temperature near the melting point of the material of the wiring layer to improve the coverage and flatness.

しかしながら、ユバツタ工程中の半導体基板21の温度
を正確に知ることが困難であるから、現状では半導体基
板21を載置するステージの設定温度とスバフタ成膜結
果との相関関係により処理を行っているが、ステージと
半導体基板21との接触状態により熱伝達の状態が変動
するので、良好な再現性を得ることが困難になっている
However, since it is difficult to accurately know the temperature of the semiconductor substrate 21 during the Yuvatuta process, the process is currently performed based on the correlation between the set temperature of the stage on which the semiconductor substrate 21 is placed and the results of the Subafuta film formation. However, since the state of heat transfer varies depending on the state of contact between the stage and the semiconductor substrate 21, it is difficult to obtain good reproducibility.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

以上説明した従来の半導体装置の製造方法においては、
半導体基板のコンタクトホールのアスペクト比が大きく
なると、コンタクトホール内に合金配線層を安定して充
填することが難しく、良好なステップ・カバレンジを持
つ配線層を形成することが困難であるという問題点があ
った。
In the conventional semiconductor device manufacturing method described above,
When the aspect ratio of a contact hole in a semiconductor substrate becomes large, it becomes difficult to stably fill the contact hole with an alloy wiring layer, and it becomes difficult to form a wiring layer with good step coverage. there were.

本発明は以上のような状況から、半導体基板のコンタク
トホール内に合金配線層が完全に充填された、ステップ
・カバレンジの良好な合金配線層を形成することが可能
となる半導体装置の製造方法の提供を目的としたもので
ある。
In view of the above-mentioned circumstances, the present invention provides a method for manufacturing a semiconductor device that makes it possible to form an alloy wiring layer with good step coverage in which the contact hole of a semiconductor substrate is completely filled with the alloy wiring layer. It is intended for the purpose of providing.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体装置の製造方法は、段差を有する半導体
基板上に合金配線層を形成する工程と、前記半導体基板
を高圧ガス雰囲気中において加熱処理する工程とを含む
よう構成する。
A method for manufacturing a semiconductor device according to the present invention is configured to include the steps of forming an alloy wiring layer on a semiconductor substrate having a step, and heat-treating the semiconductor substrate in a high-pressure gas atmosphere.

〔作用〕[Effect]

即ち本発明においては、段差を有する半導体基板上に合
金配線層を形成し、この半導体基板を高圧ガス雰囲気中
において加熱処理するから、加熱処理によってこの合金
配線層が軟化し、高圧ガスの圧力によって合金配線層が
半導体基板の段差内に圧入されるので、この段差内の合
金配線層に生じていた空間がなくなり、ステップ・カバ
レンジの良好な合金配線層を形成することが可能となる
That is, in the present invention, an alloy wiring layer is formed on a semiconductor substrate having steps, and this semiconductor substrate is heat-treated in a high-pressure gas atmosphere, so that the alloy wiring layer is softened by the heat treatment and is softened by the pressure of the high-pressure gas. Since the alloy wiring layer is press-fitted into the step of the semiconductor substrate, the space created in the alloy wiring layer within the step is eliminated, making it possible to form an alloy wiring layer with good step coverage.

〔実施例〕〔Example〕

以下第1図により本発明による一実施例を、第2図によ
り本発明による他の実施例を工程順に詳細に説明する。
Hereinafter, one embodiment according to the present invention will be explained in detail with reference to FIG. 1, and another embodiment according to the present invention will be explained in detail in the order of steps with reference to FIG. 2.

第1図に示す本発明による一実施例においては、まず第
1図(alに示すようにコンタクトホールlaを形成し
た半導体基板1の表面にスパッタ法により膜厚2μ鴎〇
M合金配線層2を形成する。
In one embodiment of the present invention shown in FIG. 1, first, as shown in FIG. Form.

このM合金配線層2の組成は、シリコンを1%含有する
アルミニウムである。
The composition of this M alloy wiring layer 2 is aluminum containing 1% silicon.

このコンタクトホール1aの直径は0.5μmで、深さ
が1μ顛で、アスペクト比が大きいから、図に示すよう
にこのコンタクトホール1aの内部にM合金配線層2に
よって封じ込められた空孔2aが形成される。
Since the diameter of this contact hole 1a is 0.5 μm, the depth is 1 μm, and the aspect ratio is large, a void 2a sealed by the M alloy wiring layer 2 is formed inside this contact hole 1a, as shown in the figure. It is formed.

このようなM合金配線層2を形成した半導体基板1をホ
ルダ5に搭載し、第3図に示すような本発明に用いる処
理装置の処理室4の中に搬入し、処理室4を密封した後
、アルゴンガスのボンベ8から圧力調節器9を経由して
500Kgf/cdのアルゴンガスをこの処理室4に供
給する。
The semiconductor substrate 1 with such an M alloy wiring layer 2 formed thereon was mounted on the holder 5, and carried into the processing chamber 4 of the processing apparatus used in the present invention as shown in FIG. 3, and the processing chamber 4 was sealed. Thereafter, 500 kgf/cd of argon gas is supplied from an argon gas cylinder 8 to the processing chamber 4 via a pressure regulator 9.

この状態で温度調節器7を用いてヒータ6に電流を流し
て昇温し、半導体基板1を550℃に加熱する。
In this state, current is applied to the heater 6 using the temperature controller 7 to raise the temperature, and the semiconductor substrate 1 is heated to 550°C.

このような加熱・加圧処理を約20分間行うと、第1図
(blに示すように半導体基板1のコンタクトホールl
a内にはM合金配線層2が完全に充填され、良好なステ
ップ・カバレンジを有するM合金配線層2を半導体基板
1の表面に形成することが可能となる。
When such heating and pressure treatment is performed for about 20 minutes, the contact hole l of the semiconductor substrate 1 is formed as shown in FIG.
The inside a is completely filled with the M alloy wiring layer 2, and it becomes possible to form the M alloy wiring layer 2 having good step coverage on the surface of the semiconductor substrate 1.

第2図に示す本発明の他の実施例においては、まず第2
図(alに示すようにコンタクトホールllaを形成し
た半導体基板11の表面に膜厚5μmのMフィルム3を
載せ、つぎに第1図の場合と同様にこの半導体基板11
をホルダ5に搭載して第3図に示す処理装置内に搬入す
る。
In another embodiment of the present invention shown in FIG.
As shown in FIG.
is mounted on the holder 5 and carried into the processing apparatus shown in FIG.

そして半導体基板11の温度を450℃に保って10分
間加熱して第2図(blに示すように半導体基板11と
Mフィルム3とを密着させる。その後温度調節器7によ
りヒータ6に流す電流を増加して半導体基板11の温度
を550℃に上昇させると、第2図(C1に示すように
半導体基板11のコンタクトホールlla内にAtフィ
ルム3の半導体基板11と接していた部分が圧入され、
半導体基板11の表面にステ・ノブ・カバレンジの良好
な配線層を形成することが可能となる。
Then, the temperature of the semiconductor substrate 11 is maintained at 450° C. and heated for 10 minutes to bring the semiconductor substrate 11 and the M film 3 into close contact as shown in FIG. When the temperature of the semiconductor substrate 11 is increased to 550° C., the portion of the At film 3 that was in contact with the semiconductor substrate 11 is press-fitted into the contact hole lla of the semiconductor substrate 11, as shown in FIG. 2 (C1).
It becomes possible to form a wiring layer with good step-knob coverage on the surface of the semiconductor substrate 11.

〔発明の効果〕〔Effect of the invention〕

以上の説明から明らかなように本発明によれば、半導体
基板の表面に合金配線層を形成した後、高圧の不活性ガ
ス雰囲気内で加熱するので、合金配線層によって封じ込
められていた空孔を合金配線層によって充填することが
可能となる利点があり、著しい経済的及び、信鯨性向上
の効果が期待できる半導体装置の製造方法の提供が可能
となる。
As is clear from the above description, according to the present invention, after forming an alloy wiring layer on the surface of a semiconductor substrate, it is heated in a high-pressure inert gas atmosphere, so that the vacancies sealed by the alloy wiring layer are removed. It has the advantage of being able to be filled with an alloy wiring layer, and it is possible to provide a method for manufacturing a semiconductor device that can be expected to be significantly economical and to improve reliability.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明による一実施例を工程順に示す側断面図
、 第2図は本発明による他の実施例を工程順に示す側断面
図、 第3図は本発明に用いる処理装置の概略構造を示す図、 第4図は従来の半導体装置の製造方法を示す側断面図、
である。 図において、 Lllは半導体基板、 la、llaはコンタクトホール、 2はM合金配線層、 2aは空孔、 3はA/フィルム、 4は処理室、 5はホルダ、 6はヒータ、 7は温度調節器、 8はボンベ、 9は圧力調節器、 を示す。 :づ/ (al スパッタ法によるM合金配線層(2)の形成〜) 加圧・加熱処理後の状態 本発明による一実施例を工程順に示す側断面図第 図 +a+ AZフィルム(3) の載置 へ) 加熱処理した状態 (cl 加圧・加熱処理した状態 本発明による他の実施例を工程順に示す便所面図本発明
に用いる処理装置の概略構造図 第 図 従来の半導体装置の製造方法を示す側断面図第 図
Fig. 1 is a side sectional view showing an embodiment according to the present invention in the order of steps; Fig. 2 is a side sectional view showing another embodiment according to the invention in the order of steps; Fig. 3 is a schematic structure of a processing apparatus used in the present invention. FIG. 4 is a side sectional view showing a conventional method of manufacturing a semiconductor device.
It is. In the figure, Lll is the semiconductor substrate, la and lla are contact holes, 2 is M alloy wiring layer, 2a is hole, 3 is A/film, 4 is processing chamber, 5 is holder, 6 is heater, 7 is temperature control 8 is a cylinder, and 9 is a pressure regulator. :/ (Al Formation of M alloy wiring layer (2) by sputtering method~) State after pressure/heat treatment Side cross-sectional view showing an example according to the present invention in the order of steps Figure +a+ AZ film (3) Toilet surface diagram showing another embodiment of the present invention in the order of steps; Schematic structural diagram of the processing equipment used in the present invention; Diagram showing the conventional manufacturing method of a semiconductor device. Side sectional view diagram

Claims (1)

【特許請求の範囲】 段差を有する半導体基板(1)上に合金配線層を形成す
る工程と、 前記半導体基板(1)を高圧ガス雰囲気中において加熱
処理する工程と、 を含むことを特徴とする半導体装置の製造方法。
[Claims] The method is characterized by comprising the steps of: forming an alloy wiring layer on a semiconductor substrate (1) having steps; and heat-treating the semiconductor substrate (1) in a high-pressure gas atmosphere. A method for manufacturing a semiconductor device.
JP2106190A 1990-01-30 1990-01-30 Manufacture of semiconductor device Pending JPH03225829A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2106190A JPH03225829A (en) 1990-01-30 1990-01-30 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2106190A JPH03225829A (en) 1990-01-30 1990-01-30 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH03225829A true JPH03225829A (en) 1991-10-04

Family

ID=12044384

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2106190A Pending JPH03225829A (en) 1990-01-30 1990-01-30 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH03225829A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5527561A (en) * 1991-05-28 1996-06-18 Electrotech Limited Method for filing substrate recesses using elevated temperature and pressure
US6218277B1 (en) 1998-01-26 2001-04-17 Texas Instruments Incorporated Method for filling a via opening or contact opening in an integrated circuit
US6329284B2 (en) 1995-10-17 2001-12-11 Mitsubishi Denki Kabushiki Kaisha Manufacturing process of a semiconductor device
KR100416815B1 (en) * 1996-12-04 2004-05-10 주식회사 하이닉스반도체 Method for forming multiple metal layer of semiconductor device
US8079131B2 (en) 2008-11-26 2011-12-20 Napra Co., Ltd. Method for filling metal into fine space

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5527561A (en) * 1991-05-28 1996-06-18 Electrotech Limited Method for filing substrate recesses using elevated temperature and pressure
US6329284B2 (en) 1995-10-17 2001-12-11 Mitsubishi Denki Kabushiki Kaisha Manufacturing process of a semiconductor device
KR100416815B1 (en) * 1996-12-04 2004-05-10 주식회사 하이닉스반도체 Method for forming multiple metal layer of semiconductor device
US6218277B1 (en) 1998-01-26 2001-04-17 Texas Instruments Incorporated Method for filling a via opening or contact opening in an integrated circuit
US8079131B2 (en) 2008-11-26 2011-12-20 Napra Co., Ltd. Method for filling metal into fine space

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