JPH03225848A - Block circuit of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To enable a fan-in capacity to be reduced and a block area to be reduced by using a transistor which is n times wider than a gate width W at a part whose load is large of an output stage and a next stage. CONSTITUTION:Compound gate elements 12-14 and an inverter 15 consist of a transistor with a gate width W of basic dimensions and an output stage logic element 16 consists of a transistor which is n times wider than the gate width W of basic dimensions, thus causing the number of elements to be reduced and area to be narrowed. Also, when a fan-in capacity which is an input capacity of a block is compared by setting the transistor with a gate width W of basic dimensions to fan-in = 1, it is equal to half the value when n is set to 2. Also, drive capacity is nearly equal, thus obtaining a circuit with a small block circuit fan-in capacity and a small block area.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to a block circuit configuration.

[Conventional technology]

Conventionally, the circuit configuration of a block that constitutes the basic functions of this type of semiconductor integrated circuit and has the same driving capacity is that when the circuit of the basic block is configured with one type of transistor width W, the output of the block is The transistor width W of the stage and the transistor @W other than the output stage were transistors having the same dimensions.

[Problem to be solved by the invention]

In the block circuit of the conventional semiconductor integrated circuit described above, when the block circuit is configured with one type of transistor width W, the transistor width W of the output stage of the block and the transistor width W of the transistors other than the output stage are the same size. Since a transistor is used, there is a drawback that the Fan-in capacitance, which is the input capacitance, becomes large. Another disadvantage is that the area of the block becomes large.

In addition, when a block is not selected due to the circuit load, there is a drawback that the block area, block delay time, and fan capacity cannot be optimized depending on whether the block is light or heavy.

An object of the present invention is to provide a block circuit that has basic functions and has the same driving capacity.
An object of the present invention is to provide a circuit with a small in capacity and a small block area. Another object of the present invention is to select A-type and B-type blocks, and reduce the block area by arranging A and B types in a mixed manner on the same chip.

The purpose of this invention is to provide a circuit that is optimized in terms of block delay time and fan-in capacity.

[Means to solve the problem]

According to the present invention, in a block circuit that constitutes the basic functions of a semiconductor integrated circuit and has the same driving capacity, transistors other than the output stage are constituted by transistors with a gate width W, and the portions with a large load in the output stage and the next stage are To obtain a semiconductor integrated circuit having a block circuit constituted by transistors having a size n times the gate width W.

Furthermore, according to the present invention, in a block circuit that constitutes the basic functions of a semiconductor integrated circuit and has the same driving ability, transistors other than the output stage are configured with transistors having a gate width of W1, and the load of the output stage and the next stage is A first block circuit constituted by a transistor having a size n times the gate width Wl and a gate l
gate, source of the first transistor of lligW2,
Each of the trains is configured by combining circuit configurations connected to the gate, source, and train of the second transistor having the gate width W2, and the gate, source, and drain of the m-th transistor, respectively. A semiconductor integrated circuit is obtained which is used in combination with a second block circuit.

In this latter type of semiconductor integrated circuit, the selection of the first and second block circuits is used when the load of the block is heavy, or when the load of the block is light and the area is desired to be small, but the speed may be slow. uses the first block circuit, and when the block load is light, uses the second block circuit.

Pretext side] Next, the present invention will be explained with reference to the drawings.

FIG. 1(a) is a logic level circuit diagram showing a first embodiment of the present invention, and FIG. 1(b) is a transistor level circuit diagram showing this first embodiment of the present invention. It is a block that constitutes a function. In this embodiment, input terminals 1, 2, 3, 4, 5゜6 of the block are composite gate elements 12, 13.
．． The inputs of the inverter 5 are connected to the outputs of the compound game controllers 12, 13, and 14, respectively.
The input of inverter 16 is connected to the output of inverter 15, and the output of inverter 16 is connected to output terminal 7 of the block.

The transistor-level circuit diagram in FIG. 1b) is a conversion of the logic-level circuit in FIG. 1a) to the transistor level. The composite gate elements 12, 13.degree. 14 and the inverter 15 are constituted by transistors having a basic gate width W, and the output stage logic element 16 is constituted by a transistor having a gate width W twice the basic dimension. A similar configuration is shown in FIG. 3(a).

As shown in (b) and (c), the conventional example is made up of 24 transistors, but this embodiment can be made up of 18 transistors, reducing the number of elements and the area. Also, the input capacity of the block is F
Comparing the an-in capacitance of a transistor with the basic dimension gate width W assuming Fan-in = 1, the Fan-in capacitance of the input terminal of the conventional block is 2",
In the case of this patent, the Fan-in capacity is "1", which is half the value. Moreover, the driving ability of the conventional technology and the present invention are almost the same.

Next, according to the second embodiment of the present invention, FIG. 1(a),
The first block circuit shown in FIG. 2(b) and FIG. 2(a),
The second block circuit shown in (b) is used in combination on the same chip. That is, the connection of the circuit of FIG. 1(a) is to the input terminal l of the block.

2.3, 4, 5.6 are composite gate elements 12, 13゜14
0 input, the input of the inverter 15 is connected to the output of the composite gate elements 12, 13, and 14, the input of the inverter 160 is connected to the output of the inverter 15, and the output of the inverter 16 is connected to the output terminal 7 of the block. ing. Note that the gate width W for 12°13.14 and 15 elements is
The inverter 16 element is composed of transistors having a size twice the gate width Wl.

The connection of the circuit shown in FIG. 2(a) is such that the gate, source, and drain of the first transistor of basic size Wl are connected to the basic size W1.
The gate of the second transistor.

The circuit configuration connected to the source and drain respectively is Pc
h) Ranjistaro pair, Nch) Ranjistaro pair and combine them to create a six-man power system.

This is a composite gate with one output.

These two types of basic blocks, which have the same function, are used together on an l chip, and when the load of the block is heavy, or even when the load of the block is light, it is desirable to reduce the area, but the speed is slow. , using the basic blocks of FIG.

In addition, when the block load is light, use the basic block shown in Figure 2, and optimize the block area, block delay time, and fan-in capacity conditions according to the block load and other conditions to create two blocks on one chip. The two basic blocks can be mixed.

FIG. 3 is a logic level circuit diagram showing a third embodiment of the present invention. The circuit connection in Figure 3 is the input terminal 1 of the block.
, 2, 3, 4, 5.6 are composite gate elements 20, 21.2
2 are connected to the inputs of the inverter, and the input of 23 is connected to the output of the composite gate element 20°21.22,
The inverter 240 input is connected to the output of inverter 23, and the output of inverter 24 is connected to output terminal 7 of the block. The composite gate elements 20, 21, 22 are made up of transistors of basic size, the inverter 23 is made of transistors of twice the basic size, and the inverter 24 is made up of transistors of twice the basic size.
consists of transistors three times the basic size. By using the above-mentioned circuit, the number of elements can be reduced compared to the circuit of the first embodiment, the area can also be reduced, and Fan-in
Capacity can be reduced.

〔Effect of the invention〕

As explained above, the present invention uses a $1iW transistor for transistors other than the output stage in a block circuit that constitutes the basic function and has the same driving capacity, and the output stage and the next stage have a large load. Gate width W in part
By using a transistor having a size n times as large as , the Fan-in capacitance, which is the input capacitance of the block, can be reduced, and the area of the block can be reduced.

In addition, by selecting the basic block based on the circuit load, etc., in a floor circuit that constitutes the basic function and has the same driving capacity, the optimum block area, block delay time, and fan-in capacity can be selected. It has the effect of being able to measure the

[Brief explanation of drawings]

FIG. 1(a) is a logic level circuit diagram showing a part of the first embodiment and second embodiment of the present invention, and FIG. 1(b) is a transistor level circuit of FIG. 1(a). Figure, Figure 2 (a
) is a logic-level circuit diagram showing a part of the conventional example and the second embodiment of the present invention, FIG. 2(b) is a transistor-level circuit diagram of FIG. 2(a), and FIG. 3 is a circuit diagram of the present invention. FIG. 3 is a logic level circuit diagram showing a third embodiment of the present invention. 1.2, 3, 4, 5.6... Input terminal, 7...
...Output terminal, 10...Power supply terminal, 11.
...GND terminal, 12, 13.14...
Composite gate device using single configuration transistor, 1
5.16... Inverter using double configuration transistors, 17° 18.19... Composite gate element using double configuration transistors, 20, 21.2
2...Composite gate element using a single configuration transistor, 23...Inverter using a tuple configuration transistor, 24...Inverter using a triple configuration transistor.

Claims (1)

[Claims] 1. In a block circuit that constitutes a basic function and has the same driving capacity, transistors other than the output stage are composed of transistors with a gate width W, and the transistors in the output stage and the next stage with large loads are 1. A block circuit of a semiconductor integrated circuit, characterized in that it is constituted by a transistor having a size n times the gate width W. 2. In a block circuit that constitutes a basic function and has the same driving ability, transistors other than the output stage are composed of transistors with a gate width W1, and portions with large loads in the output stage and the next stage have the gate width W1. Each of the gate, source, and drain of the first block circuit constituted by transistors having a size n times larger than W1 and the first transistor having a gate width W2 has a second block circuit having a gate width W2.
gate, source, drain and mth transistor of
By combining the circuit configurations connected to the gate, source, and drain of the second transistor,
A block circuit of a semiconductor integrated circuit, characterized in that it is used in combination with a configured second block circuit.