JPH03225966A - photodiode - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a photodiode constructed from an opto-electronic integrated circuit used in fields such as optical communication, ultra-high-speed information processing, and parallel information processing.

(Prior art) FE as a peripheral circuit in a photodiode
0EIC technology is known in which T and the like are integrated together.

Figure 4 is an example of this, with 4
0, the InP layer 41. InGaAs layer 42, InAlA
344. on the snAlAs layer. n-InGaAs layer 45,1
-InGaAs layer 46. p-InGaAs layer 47. p-electrode 48. A PIN photodiode region consisting of an n-electrode 49 and an InP layer 41 . InGaAs layer 42. InAlA
3 poles on snAlAs layer 50. HEM consisting of n-electrode 51
This photodiode is formed by integrating the T region and connecting the two using an electrode pattern 52 or the like. Along with the crystal growth of each layer in the photodiode region, the FET
The region is also crystal grown at the same time and then etched to form the FE.
A FET is formed except for the photodiode layer above the T region. Therefore, a step is created between the photodiode and the FET, making it difficult to form a layer by photowork or the like.

In addition, there are devices in which the photodiode and FET are flattened, and the photodiode is embedded in a semi-insulating substrate, but in this case, the FET is formed almost flat with the photodiode, but Each layer in the photodiode region and FET region must be grown separately.

Therefore, the crystal growth process becomes complicated, and sophisticated selective growth techniques are required.

(Problem to be solved by the invention) The present invention has been made in view of the above-mentioned circumstances.
By adopting an IC structure, it is possible to integrate peripheral electronic circuits in photodiodes to achieve wider bandwidth, higher sensitivity, and higher reliability, and to create elements that do not degrade the individual performance of the photodetector and electronic elements during fabrication. An object of the present invention is to provide a photodiode having a structure.

(Means for Solving the Problems) The present invention provides a photodiode region and an F on a semiconductor substrate.
In the photodiode provided with an ET region, at least a light absorption layer for the photodiode region;
It is characterized in that an active layer, a protective layer, and a contact layer for the FET region are provided in that order in common to both regions.

(Function) The present invention provides a semiconductor substrate with a photodiode region and an F
In the photodiode provided with an ET region, at least a light absorption layer for the photodiode, an FET
an active layer, a protective layer, and a contact layer for
By providing this in common to both regions, there is no difference in level between the photodiode region and the FET region, and the crystal can be manufactured by one growth. Further, by providing the contact layer on the top layer, the contact resistance of the p-electrode in the photodiode can be reduced, and at the same time, the gate resistance can be reduced in the FET.

(Example) FIG. 1 is a cross-sectional view for explaining an example in which the present invention is applied to an InGaAs-based photodiode. In the figure, the left side is the PIN photodiode (hereinafter referred to as PIN-P
It's called D. ), the region on the right side -4= is the region of a junction field effect transistor (hereinafter referred to as JFET). 1 is incident light, 2 is a p-side electrode, 3 is an antireflection film, 4 is a SiNx surface protection film, 5 is a wiring metal,
6 is a contact layer of n-InGaAsP, 7 is n-■n
protective layer of P, 8 a layer of nInGaAs, 9 a layer of n-I
nGaAs layer, 10 is n-InP layer, 11 is semi-insulating InP substrate, 12 is Zn diffusion region, 13 is n-side electrode, 1
4 is a source electrode, 15 is a gate electrode, and 16 is a drain electrode.

The PIN-PD area will be explained.

The bottom n-InP layer 10 is a semi-insulating InP substrate 1.
It serves as a buffer layer for preventing propagation of dislocations from 1 to n-InGaAsP 9 , and at the same time serves as a contact layer for the n-side electrode 13 . The next n--InGaAs layer 9 is a light absorption layer, and the following n-InGaAs layer 8 was originally introduced as an active layer of a JFET, but for a PIN-PD, it is used for forming a pn junction. Z for
During n diffusion, it has the function of preventing rapid diffusion, has good diffusion controllability, and is effective in forming a steep pn junction. n
-InP layer 7 functions as a protective layer and is effective in reducing dark current and increasing sensitivity of the photodiode.

The n-InGaAsP contact layer 6 thereon is effective in reducing the contact resistance of the p-electrode.

Next, the JFET area will be explained.

The lowest n-InP layer 1o is a buffer layer. The next n--InGaAs layer 9 is provided as a light absorption layer of P:[N-PD, but here it functions as a buffer layer. These buffer layers have the role of blocking current flowing through the active layer of the JFET from leaking to the substrate side, and are important for obtaining good saturation characteristics in drain current-voltage characteristics. The next n-InGaAs layer 8 is
This layer serves as a current path and is called an active layer or channel layer. This layer is typically doped with n-type impurities. The n-InP layer 7 thereon is a protective layer for reducing gate leakage current. n-InGaA
By providing the sP contact layer 6, the gate resistance can be reduced and the performance of the device can be improved. A P+ region 12 for forming a gate is formed inside this contact layer 6 and protective layer 7, and its front is n
- It has entered the active layer of the InGaAs layer 8.

The contact layer 6 and the protective layer 7 are removed by etching except for the gate region, and the source and drain electrodes are placed on the surface of the active layer 8 in order to reduce the ohmic resistance, which seriously affects the performance of the FET. installed directly on top.

An example of the manufacturing process of a photodiode using the integrated circuit shown in FIG. 1 will be explained with reference to FIG.

■(A) As shown in the figure, metal organic vapor phase epitaxy (MOV)
A semi-insulating InP substrate (SI-
n-InP layer 10, n--
InGaAs layer 9, n-InGaAs layer 8, n-InP
Layer 7 and n-InGaAsP layer 6 are crystal grown.

(B) As shown in the figure, after forming a 5iNX film 17 on the surface of the n-InGaAsP layer 6 by plasma CVD method, it is used as a diffusion mask for forming the P+ region of the PIN-PD and the gate region of the JFET. , circular patterns 17a and 17b are formed on the SiNx film 17 by photowork.

(C) As shown in the figure, using the SiNx film as a diffusion mask, Zn is selectively diffused at the same time to form a pn junction in the PIN-PD and JFET parts.
form.

Note that, in FIG. 6(C), the contact layer 6. Protective layer 7. n −
The InGaAs layer 8 and the n--InGaAs layer 9 are illustrated with hatching omitted.

The relative positions of the diffusion fronts in the PIN-PD and JFET sections can be adjusted by adjusting the layer thickness of the n-InP protective layer 7.
- Simultaneous diffusion of the PD section and JFET section was made possible.

(2) Remove the SiNx film with a hydrofluoric acid etchant.

(D) As shown in the figure, in order to etch the n-InGaAsP layer 6, 3i0. A film 18 is formed, and a circular pattern 18a is produced by photowork. By selective etching, using the 5in2 film 18 as a mask, (E)
The n-InGaAsP layer 6 is etched as shown.

After etching, the SiO2 film 18 is removed.

■(F) As shown in the figure, after pretreatment, plasma CVD
A SiNx film is again formed as the surface protection film 4 by the method, and a resist 19 is applied. After that, in the JFET section, contact holes for forming source and drain electrodes are made in the SiNx surface protection film 4 by photowork, and using this as a mask, selective etching is performed until the surface of the active layer 8 is reached, and lift-off is performed. The source electrode 14 and the drain electrode 16 are formed by et al.

The p-electrode of the PIN-PD and the gate electrode of the JFET can be formed, for example, by a lift-off method, as shown in FIG. First, a resist 20 is applied on the SiNx surface protection film 4. Next, patterning is performed by photowork to form contact holes for the p-electrode of the photodiode and the gate electrode of the JFET.

With the resist remaining, an electrode metal is deposited on the entire surface to form a deposited metal layer 21. Next, when the resist is removed using a resist stripping solution, the deposited metal can be left only in the contact hole area, as shown in Figure (H).

■Next, PIN-PD and JFET are connected by mesa etching.
Perform element isolation.

(2) After mesa etching, a SiNx film is formed on the mesa etched surface by P-CVD.

(2) Form the n-side electrode 13 for PIN-PD.

[Phase] Finally, the wiring metal 5 is vapor-deposited and patterned to produce a photodiode constituted by an opto-electronic integrated circuit.

Note that the element isolation process described in ■ is similar to the SiN
This may be performed after the x film is formed.

In that case, the step of forming the SiNx film in (2) is unnecessary. Also, n(I!I
The step for forming the electrode 13 can be performed simultaneously with the formation of the source electrode and the drain electrode (2).

According to this manufacturing process, the following effects can be expected.

(2) The crystal growth process only needs to be carried out once, and the number of epitaxial layers can be reduced to three to four, which is extremely small for an integrated circuit of a PIN photodiode and FET.

(2) It is efficient because the impurity diffusion for forming the PIN-PD and JFET pn junctions is performed at the same time.

■Since most of the manufacturing processes are performed on the same plane, photowork can be carried out stably and precisely.

■The source and drain electrodes of JFET are made of n-In.
Since it is placed on the surface of the GaAs active layer, good ohmic contact can be obtained, and high-speed response or high g
Higher performance can be expected, such as m (mutual conductance).

(2) Impurity diffusion for forming the 1-pn junction of the PIN-photodiode and JFET is performed simultaneously, so thermal damage to the crystal is small.

(2) Since the contact layer is provided, the contact resistance of the p-electrode of the PIN-PD and the gate resistance of the JFET can be reduced.

(2) When n-InGaAsP is used as the contact layer, it can be used as an etching mask for the n-InP protective layer.

FIG. 3 is a cross-sectional view for explaining one element of a photodiode constructed from an opto-electronic integrated circuit according to another embodiment of the present invention. As in FIG. 1, the left side is the PIN-PD area, and the right side is the JFET area. Note that the same parts as in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted. In this embodiment, the n-electrode 13 of the PIN-PD is connected to the n-InP layer 8.
By providing the p-electrode and the n-electrode on the same plane, the p-electrode and n-electrode are formed on the same plane. Further, trenches for isolation between elements were filled with polyimide 22, and wiring metal 5 was placed thereon. Therefore, in particular, photowork can be carried out easily, and a high 12-yield can be expected.

Although the InGaAs-based photodiode has been described above, it is clear that the present invention can be applied to other types of photodiodes.

(Effect of the invention) As is clear from the above explanation, according to the present invention, the PI
Since the N-photodiode and FET are integrated on the same substrate, parasitic inductance and parasitic capacitance are reduced, making it possible to widen the band and increase sensitivity of the optical receiver. Further, by providing a contact layer, it is possible to provide a photodiode using an opto-electronic integrated circuit with improved device performance. During manufacturing, the number of epitaxial layers required for the operation of the PIN photodiode and FET is extremely small, 3 to 4, and since a common layer is used, crystal growth can be performed in one step. .

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view for explaining one embodiment of the PIN photodiode of the present invention, FIG. 2 is an explanatory diagram of the manufacturing process, and FIG. 3 is another embodiment of the PIN photodiode of the present invention. FIG. 4 is a cross-sectional view for explaining the conventional PIN
FIG. 2 is a cross-sectional view for explaining an example of a photodiode. DESCRIPTION OF SYMBOLS 1... Large radiation, 2... P-side electrode, 3... Antireflection film, 4... SiNx surface protection film, 5... Wiring metal, 6... n-InGaAsP contact layer ,7・
protective layer of n-InP, 8.layer of n-InGaAs, 9
...n-=InGaAs layer, 10.n-InP layer, 1
1... Semi-insulating InP substrate, 12... P ten region,
13...n-side electrode, 14...source electrode, 15...
- Gate electrode, 16... drain electrode.

Claims (1)

[Claims] In a photodiode in which a photodiode region and a FET region are provided on a semiconductor substrate, at least
A photodiode characterized in that a light absorption layer for a photodiode region, an active layer for an FET region, a protective layer, and a contact layer are provided in that order in common to both regions. .