JPH03218077A - Photodiode - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a photodiode constructed from an opto-electronic integrated circuit used in fields such as optical communication, ultra-high-speed information processing, and parallel information processing.

(Conventional technology) FIG. 3 shows a signal output circuit from the photodiode.

A power supply current from a bias power supply is applied to the photodiode 31 via a resistor 32, the output thereof is amplified by a preamplifier 33, and an optical receiver is configured such that an output signal is obtained through a limiter circuit 34. .

In the configuration of such a conventional optical receiver, a photodiode of a discrete component type and peripheral electronic circuits such as an amplifier are separately manufactured and combined into a hybrid. In the case of a hybrid format in which optical elements and electronic elements are individually combined, the parasitic capacitance and parasitic inductance of the mount, package, bonding wire, etc. are large, which greatly degrades high-speed signal waveforms and causes problems such as response speed and noise characteristics. The problem is that it is limited. In addition, miniaturization and
There are limits to reducing power consumption.

(Problems to be Solved by the Invention) The present invention has been made in view of the above-mentioned circumstances.
By adopting an IC structure, we aim to achieve broadband, high sensitivity, and high reliability of the light-receiving element and electronic element themselves, as well as to create a photodetector with an element structure that does not degrade the individual performance of the light-receiving element and electronic element during manufacturing. The purpose is to provide diodes.

(Means for Solving the Problems) The present invention provides a semiconductor substrate with a high-purity epitaxial layer as a lower layer, an epitaxial layer with a large band gap as a cap layer on the upper layer, and a band gap larger than the cap layer between them. It is an epitaxial structure in which an epitaxial layer doped with small impurities having a high carrier saturation velocity is formed as an intermediate layer, in which in the photodiode region, the lower layer is a light absorption layer, the intermediate layer is a contact layer, and in the FET region, the epitaxial layer is doped with impurities. is characterized in that the lower layer is a buffer layer and the intermediate layer is an active layer.

The intermediate layer can be used as a control layer during impurity diffusion.

(Function) If fc is the cutoff frequency at 3 dB of the band determined by the OCR time constant of the optical receiver consisting of the PIN photodiode and front-end amplifier, then fc = 1/2πRbCt.

Here, Rb is the bias resistance of the photodiode. Ct is the total input capacity ■, and p of the photodiode
n junction capacitance icp, gate capacitance of the first stage FET of the amplifier circuit ft
cg is given by the sum of parasitic capacitance it C s including wiring capacitance. That is, Ct = Cp + Cg + Cs On the other hand, the input-referred noise of an optical receiver increases in proportion to frequency in a high frequency region, and its proportionality constant is given by Ct2/gm. gm is the mutual conductance of the first stage FET. In addition, the frequency-independent thermal noise component is 1/
Proportional to Rb.

Therefore, in order to widen the band and reduce noise (higher sensitivity) of an optical receiver, it is important to reduce Ct and increase gm.

When a photodiode (generally a light receiving element) and an electronic element are connected individually (hybrid connection), wire bonding is used for the connection, so there is a limit to the reduction of parasitic inductance and parasitic capacitance, for the reasons mentioned above. This limits the ability to widen the bandwidth and increase the sensitivity of optical receivers.

On the other hand, a type of optical element and electronic element integrated on the same substrate is called an opto-electronic integrated circuit (OEIC).
electronic integration ci
Among them, the one that integrates a light receiving element and an electronic element is called a light receiving (or receiving) OEIC.
This OEIC does not use wires to connect optical elements and electronic elements, but uses thin and short wiring patterns formed by photolithography with a roughness on the order of 1 μm.

Therefore, since wire bonding is not used, bonding pads are unnecessary, and the wiring pattern is fine, so parasitic inductance and parasitic capacitance can be extremely small, resulting in a wide band and high sensitivity. It is possible.

(Embodiment) FIG. 1 is a cross-sectional view for explaining one element of a photodiode constructed from an opto-electronic integrated circuit according to an embodiment of the present invention. In the figure, the left side is a PIN photodiode (hereinafter referred to as PIN-PD) region, and the right side is a junction field effect transistor (hereinafter referred to as JFET) region. 1 is a large radiation beam, 2 is a p-side electrode, 3 is an antireflection film, 4
is a surface protective film, 5 is a wiring metal, 6 is an nQInP cap layer, 7 is an n-type InGaAs layer, 8 is a P+ region, 9 is an n
1-type InGaAs layer, 10 is n-type or n-type InP
layer, 11 is n ft! I1 electrode, 12 is the source electrode, 1
3 is a gate electrode, 14 is a drain electrode, and 15 is a semi-insulating InP substrate.

The PIN-PD area will be explained.

The bottom n-type InP layer 10 is a semi-insulating InP substrate 1.
It serves as a buffer layer for preventing the propagation of dislocations from the light absorbing layer 5 to the light absorption layer 9, and at the same time serves as a contact layer for the n-side electrode 1l. The next n-type InGaAs layer 9 is a light absorption layer, and the following n-type InGaAs layer 7 is originally a JFE
It was introduced as an active layer of T, but PIN-PD
It has the function of preventing fast diffusion during Zn diffusion for forming pn junction, has good diffusion controllability, and has a steep pn
Effective for forming bonds. Top layer n-type InP
The layer 6 functions as a surface protection layer together with the SiN surface protection film 4 formed on the surface by plasma CVD method,
Effective for reducing dark current and increasing sensitivity of photodiodes. The diffusion is performed by selectively etching the n-type InP cap layer 6 using a diffusion mask, and then selectively etching the n-type InGa cap layer 6.
Starting from the surface of the AS layer 7, a P region 8 is formed.

The P-side electrode 2 is placed on the surface of the diffused InGaAs layer 7 to achieve good ohmic contact.

Next, the JFET area will be explained.

The lowest n-type InP layer 10 is a buffer layer. The next n-type InGaAs layer 9 is provided as a light absorption layer of the PIN-PD, but here it functions as a puffer layer. These puffer layers have the role of blocking current flowing through the active layer of the JFET from leaking to the substrate side, and are important for obtaining good saturation characteristics in drain current-voltage characteristics. The next n-type InGaAs layer 7 is a layer that serves as a current path and is called an active layer or channel layer. This layer is typically doped with n-type impurities. Top layer n-type InP layer 6 (cap layer)
is a protective layer to reduce gate leakage current,
A P region 8 for forming a gate is formed inside this cap layer 6, and its front is made of n-type InGaA
It has entered the active layer of the S layer 7. The cap layer 6 is etched away leaving the gate region, and the source and drain electrodes are placed directly on the surface of the active layer to reduce the ohmic resistance, which has a significant impact on the performance of the FET. ing.

? FIG. 4 shows the most basic high impedance type circuit of a receiving OEIC including a PIN-PD and a JFET. In the figure,
41 is PIN-PD, 42 is JFET, V, ■8 is bias voltage, Rh is bias resistance, Vb is gate voltage, G
is the gate, D is the drain, S is the source, RL is the load resistance, VD is the drain voltage, and VoUT is the output voltage.

When the modulated optical signal is input manually to PIN-PD41,
A photocurrent corresponding to the human input signal flows through the bias resistor Rb, and the gate voltage of the JFET 42 changes according to the modulated human input signal. The result is drain current. changes according to △Ia''I-h·Rb-gm.

Here, ■. is the photocurrent of PIN-PD41, gm is,
This is the mutual conductance of JFET42.

Finally, it is taken out as a modulated output signal via the load resistor RL.

The circuit shown in FIG. 4 can be easily constructed by patterning bias resistors, load resistors, etc. on the integrated circuit described in FIG. 1.

An example of the manufacturing process of a photodiode using the integrated circuit shown in FIG. 1 will be explained with reference to FIG.

■(A) As shown in the figure, metal organic vapor phase epitaxy (MOV)
A semi-insulating InP substrate (SI-
An n-type InP layer 10, an n-type InGaAs layer 9, an n-type InGaAs layer 7, and an n-type InP layer are sequentially formed on the InP substrate 15.
Layer 6 is crystal grown.

(B) As shown in the figure, after forming a SiN film 16 on the surface of the n-type InP cap layer 6 by plasma CVD method, the SiN film 16 is used as a diffusion mask for forming the P+ region of the PIN-PD. A circular pattern 16a is created on top by photowork.

(C) As shown in the figure, the n-type InP cap layer 6 is etched using the SiN film diffusion mask as a mask.

(D) As shown in the figure, a resist 17 is deposited on the SiN film formed in step (2), and a diffusion mask for forming a JFET gate is fabricated by photowork.

(E) As shown in the figure, the resist 17 is etched off, the SiN film is used as a diffusion mask, and the PIN-PD and J
At the same time, Zn (
Alternatively, Cd) is selectively diffused to form the P+ region 8.

In addition, in FIG. 3(E), in order to make it easier to see the P+ region 8 which is the diffusion region, the cap layer 6 and the n-type InGaAs layer 7 are
, the hatching of the n-type InGaAs layer 9 is omitted.

Impurity diffusion for forming a pn junction is simultaneously performed from the active layer surface in the PIN-PD section and from the cap layer surface in the JFET section, and the position of the diffusion front is controlled by adjusting the diffusion temperature and time.

The relative positions of the diffusion fronts in the PIN-PD and JFET sections can be adjusted by adjusting the layer thickness of the n-type InP cap layer 6.
Simultaneous diffusion of the IN-PD section and JFET section is made possible.

(2) Remove the SiN film with a hydrofluoric acid etchant.

■(F) As shown in the figure, after pretreatment, plasma CVD
A SiN film is again formed as the surface protection film 4 by the method. After that, in the JFET department, S
After forming contact holes in the iN surface protective film 4 for forming source and drain electrodes, the n-type InP cap layer 6 is selectively etched using this as a mask, and the source electrode 12 and drain are etched by lift-off or the like. Electrodes 14 are formed.

The p-electrode of the PIN-PD and the gate electrode of the JFET can be formed, for example, by a list-off method, as shown in FIG. First, a resist 18 is applied on the SiN surface protection film 4. Next, patterning is performed by photowork to form contact holes for the p-electrode of the photodiode and the gate electrode of the JFET.

With the resist remaining, an electrode metal is deposited on the entire surface to form a deposited metal layer 19. Next, when the resist is removed using a resist stripping solution, the deposited metal can be left only in the contact hole area, as shown in Figure (H).

■Next, PIN-PD and JFET are connected by mesa etching.
Perform element isolation.

(2) After mesa etching, a SiN film is formed on the mesa etched surface by P-CVD.

Form the n-side electrode for PIN-PD.

■Finally, metal wiring is deposited and patterned to create a photodiode made up of an opto-electronic integrated circuit.

Note that the element isolation process described in ■ is similar to the SiN
The process may be performed after the film is formed.

In that case, the step of forming the SiN film in (2) is unnecessary. Further, the process for forming the n-side electrode for PIN-PD in [phase] can be performed simultaneously with the formation of the source electrode and drain electrode in (2).

According to this manufacturing process, the following effects can be expected.

(2) The crystal growth process only needs to be performed once, and the number of epitaxial layers can be extremely small for an integrated circuit consisting of 3 to 4 layers, a PIN photodiode, and an FET.

(2) It is efficient because the impurity diffusion for forming the PIN-PD and JFET pn junctions is performed at the same time.

■Since most of the manufacturing processes are performed on the same plane, photowork can be performed stably and precisely.

■Since the p-electrode of the PIN-PD and the source and drain electrodes of the JFET are placed on the surface of the n-type InGaAs active layer, good ohmic contact can be obtained.
High-speed response or high gm (mutual conductance), etc.
High performance can be expected.

(2) Since impurity diffusion for forming the PIN-photodiode and JFET pn junction is performed simultaneously, thermal damage to the crystal is small.

FIG. 5 is a cross-sectional view for explaining one element of a photodiode constructed from an opto-electronic integrated circuit according to another embodiment of the present invention. As in FIG. 1, the left side is the PIN-PD area, and the right side is the JFET area. Note that the same parts as in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted. In this example, the n-electrode 11 of the PIN-PD is made of n-type InGaA
By providing it on the s-layer 7, the p-electrode and the n-electrode are formed on the same plane. Furthermore, trenches for isolation between elements were filled with polyimide 20, and wiring metal 5 was placed thereon. Therefore, in particular, photowork can be easily carried out and a high yield can be expected.

Although the InGaAs-based photodiode has been described above, it is clear that the present invention can be applied to other types of photodiodes.

(Effect of the invention) As is clear from the above explanation, according to the present invention, the PI
Since the N-photodiode and FET are integrated on the same substrate, parasitic inductance and parasitic capacitance are reduced, making it possible to widen the band and increase sensitivity of the optical receiver. In addition, the number of epitaxial layers required for the operation of the PIN photodiode and FET is extremely small, 3 to 4, and because a common layer is used, crystal growth can be performed in one step. This has the effect of providing a photodiode based on

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view for explaining one embodiment of the PIN photodiode of the present invention, FIG. 2 is an explanatory diagram of the manufacturing process, and FIGS. 3 and 4 are sectional views of the PIN photodiode and FET.
FIG. 5 is a cross-sectional view for explaining another embodiment of the PIN photodiode of the present invention. DESCRIPTION OF SYMBOLS 1... Incident light, 2... Pffll electrode, 3... Antireflection film, 4... Surface protection film, 5... Wiring metal, 6
... n-type InP cap layer, 7... n-type InGa
As layer, 8...P+ region, 9-n type InGaAs
Layer, 1 0 - n-type InP layer, 11... n-side electrode, 1
2... Source electrode, 13... Gate electrode, 14...
- Drain electrode, 15... semi-insulating InP substrate.

Claims (1)

[Claims] On a semiconductor substrate, the lower layer is a high-purity epitaxial layer, the upper layer is an epitaxial layer with a large band gap as a cap layer, and between them, the band gap is smaller than that of the cap layer and the saturation velocity of carriers is lower. An epitaxial structure in which an epitaxial layer doped with a large amount of impurity is formed as an intermediate layer, and in the photodiode region, the lower layer is a light absorption layer and the intermediate layer is a contact layer, and in the FET region, the lower layer is a buffer layer. , wherein the intermediate layer is an active layer.