JPH03228352A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH03228352A
JPH03228352A JP2461890A JP2461890A JPH03228352A JP H03228352 A JPH03228352 A JP H03228352A JP 2461890 A JP2461890 A JP 2461890A JP 2461890 A JP2461890 A JP 2461890A JP H03228352 A JPH03228352 A JP H03228352A
Authority
JP
Japan
Prior art keywords
output
semiconductor
signal
pattern
output terminals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2461890A
Other languages
Japanese (ja)
Inventor
Kazuo Aoki
一夫 青木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2461890A priority Critical patent/JPH03228352A/en
Publication of JPH03228352A publication Critical patent/JPH03228352A/en
Pending legal-status Critical Current

Links

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To obtain a semiconductor device which has such a circuit pattern as easily designed for a printed board by users and which has such pin locations as appointed for output terminals by users by changing freely the connection of output signals and output terminals by changing one optional piece of exposure masks in the wafer process. CONSTITUTION:In a semiconductor integrated circuit unit which has output circuits 3, 4 including the plural number of output terminals 7, 8, the connecting situation of output signals and the output terminals 7, 8 can be changed freely by changing one optional piece of exposure masks in the wafer process. For example, in the case that a user knows that a pattern interconnection of a printed board can be done easily and the size of the printed board can be reduced if a signal or data of a signal generation circuit 1 is output from a pad 8 and a signal or data of a signal generation circuit 2 is output from a pad 7, the user requests a semiconductor manufacturer to change the locations of connecting points from 11 and 12 to 13 and 14 for a contact pattern in a semiconductor pattern layout and the semiconductor manufacturer changes a mask in a contact process at the request of the user.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明はLCD%LED、PDP等の多出力端子を有
する半導体装@(ドライバIC)に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device (driver IC) having multiple output terminals such as an LCD, an LED, and a PDP.

〔従来の技術〕[Conventional technology]

第2図は一般的な従来の半導体集積回路の構成を示す図
で、図において、(1)、(2)は信号又はデータを発
生又は記憶する信号発生回路、(3) 、 (4)は信
号発生回路(1)、(2)からの信号又はデータをそれ
ぞれ集積回路外へ出力する出力回路、(5)、(6)は
信号発生回路(1)と出力回路(3)及び信号発生回路
(2)と出力回路(4)を各々接続する配線、(7)、
(8)は出力回路(3)、(4)にそれぞれ含まnた出
力端子(パッド)である。
FIG. 2 is a diagram showing the configuration of a general conventional semiconductor integrated circuit. In the figure, (1) and (2) are signal generation circuits that generate or store signals or data, and (3) and (4) are signal generation circuits that generate or store signals or data. Output circuits that output signals or data from signal generation circuits (1) and (2) to the outside of the integrated circuit, respectively; (5) and (6) are signal generation circuits (1), output circuits (3), and signal generation circuits; Wiring connecting (2) and output circuit (4), (7),
(8) is an output terminal (pad) included in each of the output circuits (3) and (4).

次に動作について説明する。信号発生回路(1ンによっ
て生成された信号は配線(5)によって出力回路(3)
に接続さ口ているため、パッド(7)を通じて、半導体
集積回路外へ出力される。また、信号発生回路(2)に
よって生成された信号は配線(6)によって出力回路(
4)に接続されているため、必ずパッド(3)を通じて
半導体集積回路外へ出力される。
Next, the operation will be explained. The signal generated by the signal generation circuit (1) is sent to the output circuit (3) via the wiring (5).
Since the signal is connected to the pad (7), the signal is output to the outside of the semiconductor integrated circuit through the pad (7). Further, the signal generated by the signal generation circuit (2) is transmitted to the output circuit (
4), the output is always output to the outside of the semiconductor integrated circuit through the pad (3).

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来の半導体集積回路は以上のように構成されていたの
で、信号が出力さnるパッド(パッケージビン端子)は
あらかじめ決まっており、半導体装置を使用するユーザ
は、これらの決まったピン配置に従って、半導体装置間
あるいは半導体装置と他の電子部品を配線するためのプ
リント基板を設計、製作する。基本的に、半導体装置か
らの出力信号は信号を共用できる入力信号と異なり、信
号毎に専用の配線パターンが必要で、従って、プリント
基板上で配線領域を最も多く占めるのが出力信号線であ
る。
Since conventional semiconductor integrated circuits are configured as described above, the pads (package pin terminals) to which signals are output are predetermined, and the user of the semiconductor device must follow these determined pin assignments. We design and manufacture printed circuit boards for wiring between semiconductor devices or between semiconductor devices and other electronic components. Basically, output signals from semiconductor devices differ from input signals that can be shared, and require a dedicated wiring pattern for each signal. Therefore, output signal lines occupy the most wiring area on a printed circuit board. .

特に、LCDドライバ■(等の多出力端子を有する半導
体装置では、こわらを組み込むプリント基板の面積をい
かに小さくするか、配線の設計が非常に難しく、時には
、片面のみの配線パターンでは配線不可能となる場合が
あるなどの問題点があった。
In particular, for semiconductor devices with multiple output terminals such as LCD drivers, it is extremely difficult to design the wiring and how to minimize the area of the printed circuit board that incorporates the stiffness, and sometimes wiring is impossible with a wiring pattern on only one side. There were some problems, such as in some cases.

この発明は上記のような問題点を解消するためになされ
たもので、プリント基板の配線パターンを設計するユー
ザが設計しやすいように、出力端子のピン配置をユーザ
か指定できるような半導体装置を得ることを目的とする
This invention was made to solve the above-mentioned problems, and to make it easier for users who design wiring patterns for printed circuit boards, it is possible to create a semiconductor device in which the pin arrangement of output terminals can be specified by the user. The purpose is to obtain.

〔課馳を解決するための手段〕[Means for solving problems]

この発明に係る半導体装置は、ウェハプロセス工程にお
いて、露光マスクを一枚変更することによって、半導体
装置内の信号の接続を変更できるようにしたものである
In the semiconductor device according to the present invention, signal connections within the semiconductor device can be changed by changing one exposure mask in a wafer process step.

〔作用〕[Effect]

この発明における露光マスクは、ユーザの指定に従って
変更され、半導体装置内の信号の出力回路までの接続を
このマスクデータによって変更することで、半導体装置
の出力ピン配置を変更する。
The exposure mask in the present invention is changed according to user specifications, and by changing the connections to the signal output circuit in the semiconductor device using the mask data, the output pin arrangement of the semiconductor device is changed.

〔実施例〕〔Example〕

以下、この発明の一実施例を図について説明する。第1
図において、(1)、(2)は信号又(まデータを発生
又は記憶する信号発生回路、(3)、(4)は信号発生
回路(IJ 、 (2)からの信号又はデータを半導体
装置外へそれぞれ出力する出力回路、(5)、(6)、
(9)、αQは信号発生回路(1)、(2)と出力回路
(3L(4)をそれぞれ接続するための配線、Qυは配
線(5)と配線(9)が接続されていることを示す接続
点で、パターンレイアウトにおいては、αυに配線コン
タクトパターンデータが配置されていることを示してい
る。@は同様に配線(6)とaりが接続さnていること
を示す接続点、α4は配線(5)とCIりを接続する場
合、配線コンタクトパターンが配置さ口る場所を示す接
続点、0勺は同様に配線(熔と(9)を接続する場合の
接続点、(7)、(8)は出力パッドである。
An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, (1) and (2) are signal generation circuits that generate or store signals or data, (3) and (4) are signal generation circuits (IJ), and semiconductor devices that generate signals or data from (2). Output circuits that output to the outside, (5), (6),
(9), αQ is the wiring for connecting the signal generation circuits (1), (2) and the output circuit (3L (4)), and Qυ is the wiring that connects the wiring (5) and the wiring (9). The connection point shown in the figure shows that the wiring contact pattern data is placed at αυ in the pattern layout. @ is the connection point that similarly shows that the wiring (6) and a are connected. α4 is the connection point indicating the place where the wiring contact pattern is placed when connecting the wiring (5) and CI 2, 0 is the connection point when connecting the wiring (9), ), (8) are output pads.

第1図において、コンタクトパターンデータは接続点Q
η及び@に配置されており信号発生回路(1)で発生し
た信号又はデータは、配線(9ンと配線(5)が接続点
叩において接続さnているので、出力回路(3)に入力
され、出力パッド(7)を通じて半導体装置外へ出力さ
れる。同様に信号発生回路(2)で発生した信号又はデ
ータは配線αQと(6)により出力回路(4)に入力さ
れ、出力パッド(3)を通じて半導体装置外へ出力され
る。
In Figure 1, the contact pattern data is the connection point Q
The signal or data located at The signal or data generated in the signal generating circuit (2) is inputted to the output circuit (4) through the wiring αQ and (6), and is output to the outside of the semiconductor device through the output pad (7). 3) is output to the outside of the semiconductor device.

ここで、ユーザがこの半導体装置をプリント基板上に配
置配線する場合、上記の出力信号が順序が逆、すなわち
、信号発生口! (1)の信号又はデータがパッド(8
)から出力され、信号発生回路(2)の信号又はデータ
がパッド(7)から出力されていnば、プリント基板上
のパターン配線が容易になり、プリント基板の大きさ(
面積)を小さくすることが判った時、ユーザは半導体メ
ーカに、半導体パターンレイアウトにおいて、コンタク
トパターンをαυ、 C121の接続点から時、uwに
配置変更する様要求を出す。半導体メーカはその要求に
従ってコンタクト工程のマスクを変更し、出力順の変更
を可能にすることができる。
Here, when the user arranges and wires this semiconductor device on a printed circuit board, the above output signals are in the reverse order, that is, the signal generation source! (1) The signal or data on the pad (8
), and if the signal or data of the signal generating circuit (2) is output from the pad (7), pattern wiring on the printed circuit board becomes easy, and the size of the printed circuit board (
When it is determined that the contact pattern (area) is to be reduced, the user requests the semiconductor manufacturer to change the location of the contact pattern from the connection point of αυ, C121 to uw in the semiconductor pattern layout. Semiconductor manufacturers can change the mask for the contact process according to their requirements, allowing them to change the output order.

なお、上記実施例では極めて簡単な場合として2つの出
力について説明したが、出力数はもっと多数であっても
良い。
In the above embodiment, two outputs were explained as an extremely simple case, but the number of outputs may be larger.

また、接続の変更方法をコンタクトマスクデータを変更
することによって可能にした場合を示したが、これは金
属配線工程等の他の工程であっても良く、上記実施例と
同様の効果を奏する。
Further, although the case has been shown in which the method of changing the connection is made possible by changing the contact mask data, this may be done in other processes such as a metal wiring process, and the same effect as in the above embodiment can be achieved.

〔発明の効果〕〔Effect of the invention〕

以上のように従来の半導体集積回路における出力信号又
はデータと出力端子との関係(出力ピン配置ンはあらか
じめ決まっており、ユーザは決まったピン配置でプリン
ト基板のパターン配線を設計していたが、この発明によ
ればユーザの指定にヨリ、ウェハプロセスにおいて、マ
スク1枚を変更するだけで、出力ピン配置を変更するこ
とができるので、ユーザは半導体装置の出力ピン配置を
気にすることなく、プリント基板配線パターンの設計が
できるという効果がある。
As mentioned above, the relationship between output signals or data and output terminals in conventional semiconductor integrated circuits (the output pin layout was determined in advance, and the user designed the pattern wiring of the printed circuit board with the determined pin layout). According to this invention, the output pin arrangement can be changed according to the user's specifications by simply changing one mask during the wafer process, so the user does not have to worry about the output pin arrangement of the semiconductor device. This has the effect of making it possible to design printed circuit board wiring patterns.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の一実施例による半導体装置を示す回
路構成図、第2区は従来の半導体装置を示す回路構成図
である。 図において、(3)、(4Jは出力回路、(7Ji8月
ま出カバノド、(5)、(6)、 (9)、 GOは配
線を示す。 なお、図中、同一符号は同一、又は相当部分を丁す。
FIG. 1 is a circuit configuration diagram showing a semiconductor device according to an embodiment of the present invention, and the second section is a circuit configuration diagram showing a conventional semiconductor device. In the diagram, (3), (4J are the output circuits, (7Ji August output circuit, (5), (6), (9), GO are the wiring. In the diagram, the same symbols are the same or equivalent. Dice the parts.

Claims (1)

【特許請求の範囲】[Claims] 複数の出力端子を含む出力回路を有する半導体集積回路
装置であって、ウェハプロセス中の任意の露光マスク1
枚を変更することで、出力する信号と出力端子との接続
を自由に変更できることを特徴とする半導体装置。
A semiconductor integrated circuit device having an output circuit including a plurality of output terminals, the device is equipped with an arbitrary exposure mask 1 during wafer processing.
A semiconductor device characterized in that by changing the semiconductor device, the connection between output signals and output terminals can be freely changed.
JP2461890A 1990-02-02 1990-02-02 Semiconductor device Pending JPH03228352A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2461890A JPH03228352A (en) 1990-02-02 1990-02-02 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2461890A JPH03228352A (en) 1990-02-02 1990-02-02 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH03228352A true JPH03228352A (en) 1991-10-09

Family

ID=12143135

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2461890A Pending JPH03228352A (en) 1990-02-02 1990-02-02 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH03228352A (en)

Similar Documents

Publication Publication Date Title
US5396701A (en) Method for packaging an integrated circuit
CN113747658A (en) Printed circuit board connection of integrated circuits using two wiring layers
JPH03228352A (en) Semiconductor device
JPH08306734A (en) Integrated circuit device with bond pad option and method of performing bond pad option
JPS6089955A (en) Semiconductor device
JP3240376B2 (en) High density mounting method of IC
JPH0349255A (en) Sealing of semiconductor integrated circuit
JPS5814391Y2 (en) Regular rhythm pattern
JPS5922335A (en) Semiconductor device
JPS5935461A (en) Mounting system of large scale integration
JPH06120346A (en) Semiconductor integrated circuit chip automatic design method
JPS6169159A (en) Integrated circuit device
JPH01316948A (en) Semiconductor integrated circuit
JPH1187909A (en) Ic connecting apparatus and auxiliary board for connecting ic
KR0117716Y1 (en) Semiconductor package
JPH05235123A (en) Connector for lsi hardware simulation connection
JPS62172438A (en) Integrated circuit mounting method
JPS63296289A (en) Hybrid integrated circuit device
JPH104176A (en) Semiconductor integrated device
JPS59197189A (en) Printed board and lsi terminal assining system
JPH04262591A (en) Mounting system for integrated circuit
JPH04118954A (en) Multi-pin semiconductor package
JPH05326634A (en) Printed wiring board
JPH045841A (en) Semiconductor device
JP2010040760A (en) Wiring support package, wiring board, and electronic device