JPH0323665A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To reduce occupation area of a memory cell without losing accumulation capacity by providing a P-type layer at the bottom of a groove formed on a substrate and by providing three electrodes in two layers within the groove. CONSTITUTION:A P<+> layer 9 is provided at the bottom of a groove of an Si substrate 8 for separating an element. Two electrodes 4 which becomes a storage node are connected to each separate n<+> layer 1, an electrode 3 which becomes a cell plate is inserted as specified. and then two memory cells are created by one groove. This memory cell allows charge to be accumulated in both of the electrode 4. thus achieving improved integration without reducing memory capacity.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to a memory cell thereof. , [Prior Art] FIGS. 2, 3, and 4 are cross-sectional views of what is called a trench cell among conventional memory cells.

In the figure, (1) is an N-type impurity diffusion layer, and (2) is the gate part of a transfer gate transistor, which is usually made of polycrystalline silicon. , (8l is an electrode that will become a cell plate, (4) is an electrode that will be a storage node, and both are usually made of polycrystalline silicon. (sl (6) is a dielectric layer, and is an insulating film such as an oxide film or a nitride film. (γ) is the AI wiring, and (8) is the semiconductor substrate.

Next, a conventional trench cell will be explained.

In the memory cell shown in Fig. 2, the electrode (8) serves as a cell plate and the substrate (8) serves as a storage node via a dielectric layer (5), and charges are stored on the substrate (8) and the N-type impurity diffusion layer (1), }AI through the transfer gate part (2)
It is transmitted to the wiring. In Figure 3, contrary to Figure 2, the substrate (8) is the cell plate and the electrode (4) is the storage node.
Charge is accumulated in the electrode (4), and the electrode (4) is connected to the N-type impurity diffusion layer (1) of the transfer gate section (2) to transfer the charge. In Figure 4, an electrode (8) is formed between the electrode (4) connected to the N-type impurity diffusion # (1) and the substrate (8), and the military pole (8) is used as the cell plate. Charge is accumulated in both the substrate (8) and the electrode (4) to increase the storage capacity of the memory cell.

[Problem to be solved by the invention]

Trench memory cells were created for the purpose of increasing the degree of integration of semiconductor memory devices, but there was a problem in that conventional trench cells were still insufficient for achieving high degrees of integration1. [Means for Solving the Problems] A semiconductor memory device according to the present invention is made to solve the problems such as, and aims to further increase the degree of integration of semiconductor memory devices. A P-type impurity diffusion layer is formed at the bottom of a groove formed in a substrate, and two layers and three electrodes are provided inside the groove. [Operation] The memory cell of this invention reduces the amount of accumulated charge. The area occupied can be reduced without any loss.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, (1) is an N-type impurity diffusion layer, and (2) is a gate portion of a transfer gate transistor, which is usually made of polycrystalline silicon. (8) is an electrode that will become a cell plate, and (4) is an electrode that will become a storage node, both of which are usually made of polycrystalline silicon. (5) and (6) are dielectric layers, which are insulating films such as oxide films and nitride films.

(Te) is an AI wiring, (8) is a semiconductor substrate, and (9) is a P-type impurity diffusion layer.

In the memory cell of this embodiment, a P-type impurity diffusion layer (9) for element isolation is formed at the bottom of a groove in a semiconductor substrate (8), and two electrodes (4) serving as storage nodes are connected to one another. N
An electrode (8) connected to the type impurity diffusion layer (1) and serving as a cell plate is inserted as shown in FIG. 1 to form two memory cells in one groove. This memory cell, like the one shown in FIG. 3, stores charges in both the substrate (8) and the electrode (4). [Effects of the Invention] As described above, according to the present invention, , two memory cells are formed in one groove, and the charge of this memory cell is accumulated in both the electrode and the substrate, so the memory capacity is not reduced.
High integration of semiconductor memory devices can be achieved.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a trench-type memory cell according to an embodiment of the present invention, and FIGS. 2, 3, and 4 are cross-sectional views of conventional trench-type memory cells. In the figure, (1) is an N-type impurity diffusion layer, and (2) is a gate portion of a transfer gate transistor, which is usually made of polycrystalline silicon. (8) is an electrode that will become a cell plate, and (4) is an electrode that will become a storage node, both of which are usually made of polycrystalline silicon. (5) and (6) are dielectric layers, which are insulating films such as oxidized or nitride films. (γ》 is A41 wiring, (8》 is a semiconductor substrate, and (9) is a P-type impurity diffusion layer. In the figures, the same reference numerals indicate the same or equivalent parts. Figure 1) Figure 2

Claims (1)

[Claims] In a semiconductor memory device having a memory cell of one transistor and one capacitor on a semiconductor substrate, a trench is formed in the semiconductor substrate, and a first layer electrode and a first layer electrode are formed through a dielectric material along the sidewalls of the trench. Two second layer storage electrodes are formed on the first layer electrode through a dielectric, and each of the two second layer storage electrodes is connected to the diffusion layer of another transfer gate transistor, and the bottom surface of the trench is A semiconductor memory device characterized in that two memory cells are formed in one trench by forming an impurity diffusion layer and arranging the first layer electrode and the second layer storage electrode.