JPH03241918A - Signal generator - Google Patents

Abstract

PURPOSE:To generate a clock signal with high accuracy at high speed by connecting delay circuits with same performance whose delay extent is adjustable by a feedback level in cascade, taking a logic of each delay circuit output so as to vary the basic clock cycle. CONSTITUTION:An IN(O(o)) is basic clock whose period is T and every time the clock passes one stage of a unit delay circuit 1, and the clock is retarded by each T as O(1), O(2). Then the polarity and the absolute value of a control voltage Vg is adjusted depending on a phase difference TO between an output O(M) of a final M-stage inputted to an input 1 of a delay control circuit 2 and a signal IN inputted to an input 2 of the circuit 2 and the result is fed back to a unit delay circuit D(m):(m=1-M). The adjustment above is repeated to make the TO close to '0' infinitely. Thus, an accurate internal signal is generated by only supplying a simple external signal.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a signal generator that is installed in a semiconductor large-scale integrated circuit and generates a clock waveform with high precision, and particularly relates to a signal generator that generates a clock waveform with high precision. This invention relates to high-precision signal generators installed in integrated circuits such as circuits and logic analyzers.

[Conventional technology]

As a conventional example, a method for controlling the operation of a memory will be explained with reference to FIG. FIG. 13(a) shows a timing chart of input clocks and clocks used inside the memory. In the figure, there are three types of internal clocks: memory selection clock C8, sense circuit operation clock SA, and pull-up operation clock. It is PU. The shape of each clock is determined by the delay ΔtH(i
= 3.4.5), rise timing t, (j =
31.41°51), falling timing tk (k=
32.42.52). These time values must be accurate for successful memory operations. For example, each other's time margin (t4□-t31.1s□-t4
□, etc.) must be set accurately. However, as for the input clock supplied from the outside, there are many restrictions on the type of clock and timing setting accuracy of the waveform.

Therefore, a typical input clock DIN is prepared which has an 'H' level period t, an rt L' level period t2, and an access period T (T=t+tz).

Using this input clock DIN, a memory selection clock C8 which is an internal clock, a sense circuit operation clock SA,
In order to obtain the pull-up operation clock PU, for example, a circuit as shown in FIG. 13(b) is used. This is due to the series connection of m stages of delay circuits DH (j, = 1 to m) each having a delay time Δt0, the capacitive load having a delay Δtc due to charge accumulation and release, and the channel resistance of an n-channel transistor Qrl and a p-channel transistor Qp. Set the width ratio. It is configured as a series connection circuit with a rise/fall adjustment circuit for delay time Δtk. Therefore, in order to obtain an arbitrary waveform, the input clock DIN is input to this delay circuit.

In the waveform of U, the delay Δt1 from the starting point is Δ1. =Δt, Xm+Δtc+Δtk It can be expressed as

Also, the internal clock 1. and tk are finely adjusted by changing the threshold value of the transistor in the rise/fall adjustment circuit. Through these adjustments, the waveforms of the internal clocks SA, PU, and C8 described above are obtained.

[Problem to be solved by the invention]

In the above conventional technology, since the configuration of the delay circuit is fixed, (1) even if the external input clock is changed;

Problems include the inability to control the rise and fall timing, and the need to provide excessive operating margin to account for fluctuations due to ambient environmental conditions such as temperature and manufacturing technology such as threshold variations. There is, the whole @
It was difficult to control the high-speed movement of roads and lacked versatility.

SUMMARY OF THE INVENTION In order to solve the above problems, an object of the present invention is to provide a signal generator that allows internal circuits to operate accurately and at high speed without providing excessive operating margin.

[Means to solve the problem]

In order to achieve the above object, the present invention consists of: (1) connecting an arbitrary number of unit delay circuits in series whose delay amount can be externally controlled; (2) automatically controlling the delay amount during internal circuit operation; The main features are that it can be fixed, and (2) an arbitrary logic circuit is added to the output of each unit delay circuit.

[Effect]

With the above configuration, delay circuits with the same performance whose delay amount can be adjusted by the feedback potential are connected in series, and by taking the logic of the output of each delay circuit, a large number of It becomes possible to generate high-frequency clocks. Furthermore, by changing the basic clock cycle, the rise and fall times of the entire two generated clocks can be freely set.

Through the above-described operation, a high-precision and high-speed lock can be generated inside the LSI.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

Example ↓: FIG. 1 is a diagram showing a first embodiment of the present invention.

In this embodiment, the single-phase clock is input from the system input to the synchronous RA
An example of a configuration for generating an internal clock for operating M is shown.

In the second construction diagram, 1 is a unit delay circuit D(m): (m=1
~M) receives the input signal I(m) and outputs the analog signal G(
This is an element that can adjust the output timing of the output signal 0(m) depending on the input level of the output signal 0(m). 2 is a delay control circuit that detects the phase shift between the comparison signal input terminals 1nput 1 and 1nput 2, and calculates the lead/lag of this phase difference ΔT as the output voltage V,! This is a circuit that converts the increase or decrease of . 3 is a negation element that outputs the negation of input iv to Ov, 4 is input i
a logical sum element that outputs the logical sum of rl and ir2 to orl;
5 is input ial.

AND element that outputs the AND of ia2 to oal, 6 i
! This is an AND element that outputs the AND of inputs ia3 and ia4 to oa2.

The unit delay circuits D(m) with code 1 are connected in series from m=1 to M, and the external input terminal IN (or 0(o)) is connected as follows.
Input end chain (1) of D (1), which is the starting point of the cascade-connected unit delay circuit, and 1nput 2 of delay control circuit 2
Connect ○(k) to I(k+1) (k=1~M-1)
The output 0(M) of the final stage D(m) is connected to 1nput 1 of the delay control circuit 2.

Also, connect O(o) to the input irl of the logical sum element 4, the input iv of the negative element 3, and the input ial of the logical product element 5,
0(1) is connected to the input ir2 of OR element 4, and 0(5
) as input ia2 of AND element 5 and input i of AND element 6
a4, and the output ov of the NOT element 3 is connected to the input ia3 of the AND element 6. For convenience, the output o of the OR element 4 is
rl is the memory selection clock C8, and the output o of the AND element 5
Let al be the sense circuit operation clock SA, and the output oa2 of the AND element 6 be the pull-up operation clock PU.

Here, in FIG. 2 which shows a specific configuration example of the unit delay circuit D(m) in FIG. 1, Ml and M2 are n
It is a channel transistor.

M3 to M5 are p-channel transistors.

By connecting Ml, M3, and M5, the delay control negation element is connected to M2,
Negation elements are formed by connecting M4.

When these are connected in series and a signal I(m) is input, the signal I(m) is outputted with a delay. At this time, if the voltage of the signal G(m) applied to the gate of M5 is changed, Ml
, M3, M5, the logic thresholds of the negative element outputs change,
The falling timing of output ○(m,) is shifted, and D(m,)
) The delay per element can also be controlled.

Next, a specific configuration example of the delay control circuit 2 shown in FIG. 1 is shown in FIG. 3. In the figure, D(m) is equivalent to the delay element shown in FIG. 1, and the entire M stages form the reference signal generation circuit DG.

SRI and SR2 are S/R latches, which store and output "1(H") at the falling timing of the signal to the S terminal, and
This is an element that stores and outputs "L" at the falling timing of a signal to a terminal. M1 to M7 are n-channel transistors, A1 to A4 are constant current sources, C1 to C5 are capacitors, and SA
is a differential amplifier. These are controlled by a sequencer S. The sequencer S is formed of a counter, and generates four types of signals elk 1 to elk 4 having a period of 4T and having a phase shift of 1 T from a reference signal Tin of 1 period T, as shown in FIG.

The operation of the circuit system shown in FIG. 3 will be briefly explained below. That is, the capacitances C1 and C2 are increased by the signal elk l.
The delayed signal of elk 2 starts to be transmitted in the reference signal generation circuit DG by the signal clk 2, and at the same time, the outputs of SRI and SR2 become 1 (from L 7+ to rtH), and the capacitors C1 and C2 are charged. Start ■signal elk
3, the output of SR2 changes from “H” to “L”,
Stop charging by SR2.

■The output of the SRI changes from rtH" to jlL" by the output of the reference signal generation circuit DG, charging by the SRI is stopped, and the voltage difference proportional to the amount of charge in the capacitors C1 and C2 is amplified by the differential amplifier SA. , ■ The resistance values of n-channel transistors M6 and M7 are set according to the output level of differential amplifier SA, ■ signal elk 4 charges or discharges capacitor C3 via n-channel transistor M3, and control voltage ■ 5 is set. Occur. The control voltage V9 is controlled by constantly repeating the above steps (1) to (2).

FIG. 5 shows an example of the operating waveforms in FIG. 1. Here, the basic operation is as follows. That is, ■IN(0(o
)) is a basic clock with one period T. Every time this clock passes one stage of unit delay circuit l, 0(1), o(
2), it propagates with a delay of ΔT.

■The control voltage v,
By adjusting the amount and absolute amount of J, unit delay circuit D(m):
(m=1 to M).

Repeat the above steps and (2) to bring ΔTo as close to O as possible. At this time, the value of ΔT is the arbitrary m-th stage output and m+
The output difference with the first stage is expressed as ΔT=T/M (1).

Therefore, the waveform generated by the circuit shown in the engineering drawing is as follows.

The waveforms are as shown in C5, SA, and PU in FIG.

The clock margin on the memory side is 10. 11,
Although values such as L2 and t must be guaranteed, by using the circuit of this embodiment shown in FIG.
is 5×ΔT, t is T/2-6XΔT, t2 is ΔT,
t can be defined as O and can be kept constant regardless of the environment, transistor performance, or changes over time.

Example 2: FIG. 6 is a diagram showing a second embodiment of the present invention.

This embodiment shows an example of a configuration in which a clock for an asynchronous memory is generated using the delay circuit and delay control circuit shown in the first embodiment.

As explained above in the embodiment, the unit delay circuits 1 and D
(m): (m = l to M), delay control circuit 2.
The signal IN generates an output voltage V such that D(m) - the delay amount ΔT per stage becomes T/M. On the other hand, D
Unit delay circuit 7, which is an element equivalent to (m), D'(n)
: (n = 1 to N) are connected in cascade and Vg is applied to G'(n) of D'(n). The outputs of D'(n) are each set to O(n), and an arbitrary logic circuit is connected. In this embodiment, as an example, similarly to the first embodiment, the negative element 3
, logical OR element 4. AND elements 5 and 6 are connected.

An example of the operating waveforms of this circuit is shown in FIG. Here, IN is a synchronization signal with period T, and CLK is the period of IN and an arbitrary value ΔT.
This is a single signal shifted by 1. D'(n
) output 0(n ) is the output 0(n ) of D'(n - engineering)
-1) and delayed by ΔT with respect to signal CLK.
The signal is delayed by Xn. Therefore, CS, SA, P
U performs an cycle operation for a single signal CLK that is arbitrarily input. These signals are ideal as control clocks for asynchronous memories.

Example 3: FIG. 8 is a diagram showing a third embodiment of the present invention.

This embodiment shows an example of a configuration in which the delay circuit and delay control circuit shown in the first embodiment are used to operate as a word generator.

Similar to the first and second embodiments, the unit delay circuits 1 and D
(m): (m=l ~M), delay control circuit 2, signal I
By N, D(m) - delay amount per stage ΔTfJ<T
An output voltage V8 of /M is generated. In the following description, for convenience, it is assumed that M=8, but this may be any number. 8 is a memory element that stores data for l pits, M (m
): (m=1 to 8), and is composed of ROM, RAM, registers, etc. The stored data in M (m) is D
Due to the output 0(m) of (m), O'(m): (m =
i to 8). Therefore, the circuit M consisting of M(m) may be a general memory circuit. D' denoted by 9
(m): (m = 1 to 8> is a delay element that has delay controllability equivalent to D(m) and whose output is inverted.D
'(m) delay amount control terminal G' (m) has D(m
), and simultaneously controls the delay amount ΔT and synchronizes the signals. A (m
) is an AND element that outputs the AND of two input values.

R1, denoted by reference numeral 11, is the output signal 0'(
m) is an OR element that receives as input.

The operation of these circuits will be explained below. Due to the output 0 (m) of D(m), the data stored in M(m) is output to 0' (m). ○'(m) is D'(m
) to the input terminal of A(m), and D'(m) to the input terminal of A(m).
) are respectively connected to input terminal 2 of A(m), and when the stored value 1/H11 is output to O'(m), only during the delay time ΔT of D'(m).

u Hre appears in ○'(m). On the other hand, 0
When the stored value of '(m) is "L", O'(m) is fixed to t(L"). R1 takes the logical sum of the output of A(m) and outputs it to CLKOUT.

FIG. 9 shows an example of the operating waveform of the circuit in FIG.
Output to O'(m) with a time width of T. ○The output of #(m) is the transmission order of the signal of D(m), that is, the chronological order of R
1, a waveform according to the stored information appears at CLKOUT.

In this way, an on-chip possible word generator can be constructed.

Embodiment 4: FIG. 10 is a diagram showing a fourth embodiment of the present invention, in which the same functions as those of the third embodiment are provided in a separate circuit.

In the figure, D(m): (m=1 to 8) is the input signal I
(m) and analog signals G (m) and G'(m)
: (m=1 to 8) is an element that can adjust the falling and rising timings of the output signal 0(m) depending on the input level. 12 is a rise delay control circuit, and has an input terminal 1nput 1' equivalent to the delay control circuit 2.
, 1nput 2', and is a circuit that detects the difference in rise timing and converts it into an increase/decrease in the output voltage v,'. Delay control circuit 2. The memory element 8 and the OR element 11 are the same circuits as in the third embodiment.

In FIG. A specific example of the configuration of D(m) is shown in the 11th
As shown in the figure, Ml, M2. M6 is an n-channel transistor, and M3 to M5 are p-channel transistors. Ml,
M3. M5. M6 is connected to a delay control negation element, M2. M
A negative element is formed by connecting 4. When these are connected in series and a signal I(m) is input, it is output to O(m) with a delay.

At this time, if the voltage of the signal G(m) applied to the gate of M5 is changed, Ml, M3, M5. The logic threshold of the negative element output of M6 changes, the rise timing of the output ○(m) is shifted, and the fall delay per element of D(m) can be controlled. Furthermore, when the voltage of the signal G'(m) applied to the gate of M6 is changed, 'M1. M3. M5
- The logic threshold of the negative element output of M6 changes, the fall timing of output 0(m) is shifted, and the rise delay per element of D(m) can be controlled.

A specific example of the configuration of the rise delay control circuit 12 in FIG. 10 is shown in FIG. 12. The difference between this and the delay control circuit 2 is the input polarity of SRI and SR2, which are the input circuits of 1nput↓' and 1nput2'.

That is, SRI and SR2 of the delay control circuit 2 are as follows.

The fall delay time of D(m) is controlled by the fall timing of DG output, elk2, and elk3.
In the rise delay control circuit 12, the output of DG.

At the rising timing of elk 2 and elk 3, D
(m) The rise delay time is controlled.

In this example, the rising edge of the output 0(m) of D(m)
As a result of controlling the falling timing by the delay control circuit 2 and I2, the falling timing used in the third embodiment is ! ll11 D' (m), A (m)
elements become unnecessary.

〔Effect of the invention〕

According to the present invention, by combining a self-controllable control circuit and conventional logic elements on an LSI chip, accurate internal signals can be generated by simply applying external signals. As a result, (i) it is affected by substrate temperature and aging in the same way as controlled elements, so it can be stably controlled over a long period of time.

(n) Compared to applying signals from outside, waveforms are not distorted by loads or buffers.

No special conditions of use required.

(iii) A high-speed signal can be supplied to the limit of device performance.

There are advantages such as

The signal generator of the present invention is highly effective when used in control signal generation circuits for high-speed LS such as parallel processing processors and high-speed memories such as cache memories.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention, FIGS. 2 and 3 are diagrams showing an example of a circuit for realizing the embodiment, and FIG.
The figure is a control waveform diagram, and FIG. 5 is an operation waveform diagram in this embodiment. FIG. 6 is a circuit diagram of the second embodiment of the present invention, and FIG.
The figure is an operational waveform diagram in this embodiment. FIG. 8 is a circuit diagram of a third embodiment of the present invention, and FIG. 9 is an operational waveform diagram in this embodiment. FIG. 1O is a circuit diagram of a fourth embodiment of the present invention,
FIGS. 11 and 12 are diagrams showing an example of a circuit for realizing the fourth embodiment. FIG. 13 is an explanatory diagram of a conventional example. Explanation of symbols 1... Unit delay circuit 2... Delay control circuit 3.
...Negation element 4...Order element 5.6...
・Logic product element 7...Unit delay circuit 8...Storage element 9゛°delay element 10...Logic product element
11...OR element 12...rise delay control circuit t51t52 (0) Fig. 13

Claims (1)

[Claims] 1. A delay element whose delay amount can be controlled by an external control signal, a clock transfer device which can take out an output from each stage in which n stages of delay elements with uniform characteristics are connected in series, and a period T.
Compares an arbitrary external input clock with a clock output that has passed through the clock transfer device using the external input clock as input, generates a control signal such that the total delay amount of the clock transfer device is one cycle, and controls the delay element n. Generates an arbitrary clock whose rise and fall timings are defined with a time accuracy of T/n using a control circuit that can be supplied to each stage and any plurality of clock outputs among the n clock outputs of the delay element. A signal generator characterized in that it has a circuit.