JPH03250225A - Logical simulation environment setting method - Google Patents

Abstract

PURPOSE:To eliminate the need for the preparation of a test instruction string or an initial environment setting condition at every logical simulation object by providing a means to set the converted test instruction string and the initial environment setting condition on a logic simulator. CONSTITUTION:A data file read part 4 reads out a test instruction train 200 for logical simulation stored by a data input part 2 and RAM initial value data 300 at the time of test instruction string execution from a data file group 11 and delivers the data to data conversion parts 51-5n corresponding to hardwares as the objects of the logical simulation. The data conversion parts 51-5n convert the prepared test instruction string 200 for logical simulation and RAM Initial value data 300 at the time of the test instruction string execution to the data specification of the hardwares as the objects of logical simulation. Thus, without preparing the test instruction string and initial environment setting condition depending on the internal specification of the logical simulation objects, logical inspection can be executed with high performance and high accuracy by stored and controlled logical inspection resources.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a logic simulation environment setting method that reuses logic verification assets when logic verification is performed using a logic simulator.

[Prior art]

Conventionally, when performing detailed logic verification using a logic simulator, logic simulation test instruction sequences and logic simulation initial environment setting conditions have been individually created in accordance with the internal specifications of the logic simulation target.

In addition, as a known document of this type, Japanese Patent Application Laid-Open No. 1-20954
Publication No. 2 is mentioned.

[Problem to be solved by the invention]

The above conventional technology does not take into consideration the fact that multiple logic simulation targets with different internal specifications are verified using a logic simulator, and the logic simulation test instruction sequence corresponding to the logic configuration to be the logic simulation target and logic simulation initial stage are not considered. There was a problem in that each environment setting condition had to be created individually.

The present invention has been made to solve the above problems.

An object of the present invention is to provide a logic simulation environment setting method that does not require creating a test instruction sequence and initial environment setting conditions for each logic simulation target.

[Means to solve the problem]

In order to achieve the above object, the present invention provides a means for creating and storing a logic simulation test instruction string and logic simulation initial environment setting conditions in a format that does not depend on the specifications of the object of logic simulation, and a means for creating and storing a logic simulation test instruction string and logic simulation initial environment setting conditions, and This is achieved by having means for converting initial environment setting conditions into specifications for a logic simulation target, and means for setting the converted test instruction sequence and initial environment setting conditions in a logic simulator.

[For production]

According to the above-mentioned means, by creating, storing, and managing test instruction sequences and initial environment setting conditions in a format that does not depend on the internal specifications of the logic simulation target, logic verification of the logic simulation target designed with different internal specifications is possible. When performing a logic simulation, it is possible to perform high-performance, high-precision logic verification using accumulated and managed logic verification assets without creating test instruction sequences and initial environment setting conditions that depend on the internal specifications of the logic simulation target.

〔Example〕

Hereinafter, one embodiment of the present invention will be specifically described using the drawings.

Fig. 1 is a diagram showing the overall configuration of a logic simulation environment setting method according to an embodiment of the present invention, Fig. 2 is a diagram showing a test instruction string for logic simulation, and Fig. 3 is a diagram showing the test instruction string execution time. Figure 4 showing RAM initial value data of
．． FIG. 5 is a diagram showing an example of data created for hardware to be subjected to logic simulation.

In FIG. 1, the host computer engineer has a data input section 2,
System control unit 3. It is composed of a data file reading section 4, data converting sections 5l-5n, and a fa-coupling simulator control 6. Furthermore, this host computer 1 includes a logic simulator 7, a keyboard 8, a TSS terminal 9, and a printer! 0. A data file group 11 is connected.

The data input unit 2 displays a man-machine interface screen on the TSS terminal 9 and, through conversation with the operator, inputs a logic simulation test instruction string 200 and RAM initial value data 300 (programmable registers, memory and hardware registers, memory)
is created and updated, and the created data is stored in the data file group 11.

The data file reading unit 4 reads the logic simulation test instruction sequence 200 accumulated by the data input unit 2.
and RAM initial value data 300 when executing a test instruction string
is read from the data file group 11, and the data conversion unit 51 =
Pass the data to 5n.

At this time, the operator instructs the selection of hardware to be subjected to logical simulation.

The data conversion units 51 to 5n convert the created logic simulation test instruction string 200 and the RAM initial value data 300 at the time of execution of the test instruction string into data specifications of the logic simulation target hardware.

Data setting to hardware RAM excluding memory and cache memory is performed using elements 3 necessary for creating hardware RAM data of hardware to be subjected to logic simulation from among RAM initial value data 300 during test instruction sequence execution.
01 to generate data, and a method of setting a setting instruction bit at a designated location 201 in a test instruction string for logic simulation.

Data can be set in the memory and cache memory by setting the setting instruction bit at a specified location 202 in the test instruction string for logic simulation, and by setting the instruction and data when the test instruction string is executed as described above. This is done by specifying 302 as RAM initial value data.

Even if the logic simulation test instruction sequence 200 used and the RAM initial value data 300 at the time of test instruction sequence execution are the same, the data after conversion is generated using different data conversion units 51 to 5n. The data in the hardware RAM, memory, etc. will be different.

Figure 4 shows the data flow when the simulation target hardware is model A, and the data 400 converted for model A, and Figure 5 shows the data flow when the simulation target hardware is model B. , respectively show data 500 converted for model B.

The data 400 converted for model A and the data 500 converted for model B are different, but from the perspective of each logic simulation target hardware, they have exactly the same content, and the data 500 converted for model A are different. When simulating model A using data 400 and when simulating model B using data 500 converted for model B, the same behavior must be performed on the hardware to be simulated. I can do it.

The logic simulator control unit 6 writes the data converted by the data conversion units 51 to 5n into the RAM inside the logic simulator 7 according to a predetermined procedure, and stores the written data in the TSS.
Output to terminal 9 and printer 10.

〔Effect of the invention〕

As explained above, according to the present invention, there is no need to create test instruction strings and initial environment setting conditions for each logical simulation target, and it is also possible to centrally manage test instruction string data and initial environment setting condition data. Become.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the overall configuration of a logic simulation environment setting method according to an embodiment of the present invention, and FIG. 2 is a diagram showing a test instruction sequence for logic simulation. FIG. 3 is a diagram showing RAM initial value data at the time of execution of a test instruction sequence, and FIGS. 4 and 5 are diagrams showing an example of data created for logic simulation target hardware.

Claims (1)

[Claims] 1. In a simulation method that performs logic verification using a logic simulator, a means for creating and storing a logic simulation test instruction sequence and logic simulation initial environment setting conditions in a format that does not depend on the specifications of the logic simulation target, and a test created by the method A logic simulation environment setting comprising means for converting an instruction string and initial environment setting conditions into specifications for a logic simulation target, and means for setting the converted test instruction string and initial environment setting conditions in a logic simulator. method.