JPH03250490A - Memory circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to memory circuits such as dynamic RAM and static RAM that require high-speed operation.

(Prior art) In memory circuits such as dynamic RAM and static RAM, the larger the number of integrated memory cells, the longer the signal transmission delay time to the memory cells located at a greater distance from the signal supply side. There is a problem with becoming.

FIG. 4 is a circuit diagram showing the configuration of a conventional memory circuit.

Reference numeral 41 denotes a memory cell matrix, which is composed of a plurality of word lines 42 and bit lines 43 that intersect in a matrix, and memory cells 44 provided at each intersection of the word lines 42 and bit lines 43. Each memory cell 44 is supplied with each signal of the word line 42 and bit line 43. 45 is a row decoder, which selects one decode line 46 out of a plurality of lines according to an address. 4
7 is an AND gate circuit, which connects the decode line 46
The output of the word line select signal φWS is input, and the output is supplied to the word line 42. 48 is a precharge circuit, and all bit lines 43 are precharged by a precharge signal φPR. 49 is a sense amplifier, and the memory cell 4 is
Confirm the contents of 4. A column decoder 50 outputs data held by the memory cells 44 in the memory cell matrix by the sense amplifier 49 according to the address.

The operation of the read system of the circuit shown in FIG. 4 will be explained with reference to the timing chart shown in FIG.

First, the precharge signals φ and R change from “1” level to “0” level.
” level, all bit lines are precharged to high level (Voo).Next, the signal on one decode line 46 selected by the row decoder 45 is the word line select signal φW5. is supplied to one word line 42 via the AND gate circuit 47. At this point, the information written in the memory cell 44 changes from the "O" level to the "1" level.
If it is 1', the bit line holds VDD, and if it is "0", the bit line drops from VDD by the voltage corresponding to the memory cell.Next, the sense amplifier signal φSA changes from the "O" level to "1". ° By changing the level, the sense amplifier 49 changes the data on the bit line 43 to “O” or “
1°, and is selected and output by the column decoder according to the above address.

One factor that affects the speed of the read operation is the delay time during which a signal is transmitted via the word line. Generally, aluminum is used for the bit line 43 in FIG. 4, and polysilicon is used for the word line 42. Polysilicon has a sheet resistance of 500~ compared to aluminum.
It's 1000 times bigger. Therefore, a transmission delay of the word line select signal φws occurs.

That is, the signal transmission delay time to the memory cell located at the position a where the distance from the supply side of the signal φws is the greatest is, for example, 1. in FIG. ．． 12. This 1+
(or t2) is 2 out of 1 cycle of operation.
It occupies about 0% of the time.

In such a memory circuit, it is necessary to provide a sufficient margin for the delay time indicated by tI+t2 in this one cycle operation. If not, for example, after the memory cell at position a is selected by the word line, the bit line is precharged and unrelated data is written to this memory cell before it becomes completely "0" level. This is because there is fear.

(Problems to be Solved by the Invention) As described above, in conventional memory circuits, the signal transmission delay time to memory cells located at a large distance from the signal supply side is long, and the margin time for the transmission delay is 1. This has the drawback that it occupies a considerable amount of time in the cycle of operation, which hinders improvement in operation speed.

The present invention has been made in consideration of the above circumstances, and an object thereof is to provide a memory circuit that reduces signal transmission delay time and improves operating speed.

[Structure of the Invention (Means for Solving the Problems) The memory circuit of the present invention is configured such that a control signal is supplied to the word line and the bit line at a predetermined timing, and the memory circuit is controlled by the word line signal and the bit line signal. A memory cell array formed by arranging memory cells made up of respective storage elements in a matrix is connected between each of the word lines and a first potential, and is supplied with a word line signal to select a selected word line. It is composed of a discharge circuit that discharges the potential at a predetermined timing.

(Function) In this invention, the discharge circuit newly connected to the word line shortens the falling propagation delay time of the word line.

(Examples) Hereinafter, the present invention will be explained by examples with reference to the drawings.

FIG. 1 is a circuit diagram showing a configuration according to an embodiment of the present invention. In the circuit configured as shown in FIG. 4, the row decoder 45
A new discharge circuit 11 is added to the end of the word line 42 on the opposite side.

Note that in FIG. 1, the same parts as in the circuit of FIG. 4 are given the same reference numerals.

This discharge circuit]1 is provided with one N-channel MOS transistor 12 between each word line 42 and the ground potential VSS at the end of the memory cell array, and a word line select signal φ7 is connected to the gate of this transistor 12. ．． The configuration is such that an inverted signal of is commonly supplied via the inverter 13.

The operation of the read system of the memory circuit having the above configuration will be explained with reference to the timing chart of FIG.

By changing the precharge signals φ and R from the "1" level to the "0" level, all bit lines are precharged to high level (V DD). At this time, all word line select signals φ and must be at the "0" level. In this invention, when the word line select signal φws changes from level "1" to level "02," the word line select signal φws is transmitted through the inverter 13.
An inverted signal of , that is, a “1” level is supplied to the discharge circuit 11 . This allows each N-channel MO
S transistor ] 2 is turned on, and the selected word line 42
The level of is discharged from both the row decoder 45 side and the discharge circuit 11 side. Therefore, the discharge time of the word line 42 is reduced to about half of the conventional one.

After the precharge signal φPR changes to “1” level,
The signal of one decode line 4C selected by the row decoder 45 is that the word line select signal φ6 is “0”.
By changing from level to “1” level, AND
It is supplied to one word line 42 via a gate circuit 47. At this time, the discharge circuit 11 is supplied with an inverted signal of the signal φw5 at the "0° level" through the inverter 13, so each transistor 12 in the discharge circuit 11 is turned off.

Here, as in the conventional case, if the information written in the memory cell 44 is "1", the bit line holds VDD and "
0", the bit line drops from vDD by the voltage corresponding to the memory cell. Next, the sense amplifier signal φS^
changes from the “0” level to the “1” level, the sense amplifier 49 changes the data on the bit line 43 to “0”.
It is determined as "or", and is selected and output by the column decoder according to the above address.

According to the circuit of the above embodiment, as shown in FIG.
After the signal φws falls, the precharge signals φ and R
The timing of changing from the "1 degree level" to the "0" level is t compared to the conventional tl.

This makes it possible to shorten the operating time of one cycle.

FIG. 3 is a circuit diagram of a configuration showing an application example of this invention,
The discharge circuit 11 shown in FIG.
In addition to the end of word line 2, the word line 42 is also provided in the middle of the word line 42, so that an inverted signal of the word line select signal φ6 is commonly supplied via the inverter 13.

According to the configuration shown in FIG. 3, the discharge time for the level of the selected word line 42 is shortened to about 1/4 of the conventional level.

The signal transmission delay time on the word line increases as the number of memory cells increases, that is, as the number of memory cells in the word line direction increases. In this way, by increasing or decreasing the number of locations where the discharge circuit 11 is provided depending on the length of the word line (the number of memory cells), a high-speed operation memory circuit with reduced discharge time can be realized.

In addition, the discharge circuit II has a simple configuration in which only one N-channel MOS transistor 12 is provided between each word line 42 and the ground potential Vss, and the circuit can easily provide a margin in design. It has the advantage of being possible.

Note that in this invention, there is no particular limitation on the memory cell, and as long as a circuit is configured to discharge the word line signal after being selected, even a dynamic type memory cell can be used.
It can also be a static type.

〔Effect of the invention〕

As described above, according to the present invention, by providing a discharge circuit, it is possible to provide a memory circuit that shortens the signal transmission delay time on the word line and improves the operating speed.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a configuration according to an embodiment of the present invention, and FIG.
FIG. 3 is a timing chart showing the operation of the circuit shown in FIG. 1, FIG. 3 is a circuit diagram of a configuration according to an application example of the present invention, and FIG. 4 is a circuit diagram showing the configuration of a conventional memory circuit. FIG. 5 is a timing chart showing the operation of the circuit of FIG. 4. 11...Discharge circuit, 12...N channel M
OS transistor, 13... Inverter, 41...
Memory cell array, 42...word line, 43...bit line, 44...memory cell, 45...row decoder, 46...decode line, 47...AND gate circuit, 48...prior Charge circuit, 49...Sense amplifier, 50...Column decoder.

Claims (2)

[Claims] (1) A memory in which control signals are supplied to word lines and bit lines at predetermined timing, and memory cells each consisting of a storage element controlled by these word line signals and bit line signals are arranged in a matrix. The present invention is characterized by comprising: a cell array; and a discharge circuit connected between each of the word lines and a first potential, to which a word line signal is supplied and discharges the potential of a selected word line at a predetermined timing. memory circuit. (2) A memory circuit characterized in that the discharge circuit is provided every plural number of memory cells in the length direction of each word line.