JPH07114793A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To shorten the time for lowering voltage of a word line from a selecting level to a non-selecting level, while reducing a chip area. CONSTITUTION:A word line booster circuit 2 is arranged closely to one end of a X decoder 3. A boosting signal line LphiRA is arranged from one end to the other end of the X decoder 3. A boosting signal phiRA is supplied from one end of the boosting signal line LphiRA. A word line lowering circuit 6 which makes a lowering current flow through a ground wiring GND2 is provided closely to the other end of the X decoder 3. Lowered voltage is simultaneously applied to the boosting signal line LphiRA from one end of the boosting signal line LphiRA by a lowering section 22 in the word line boosting circuit 2 through a ground wiring GND1 and from the other end of the boosting signal line by the word line lowering circuit 6 through the ground wiring GND2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
In particular, the present invention relates to a semiconductor memory device including a word line boosting circuit that boosts a word line at a selected level to a level higher than a power supply potential.

[0002]

2. Description of the Related Art In a dynamic RAM type semiconductor memory device using a memory cell consisting of one transistor / one capacitor, a word line selection level is a power supply potential Vc.
In the case of c, if the threshold voltage of the transistor of the memory cell is Vt when the write data is at a high level, only the level of (Vcc-Vt) can be written in the memory cell, and when this is read. Digit line potential Vd
Is as follows.

Vd = (Vcc−Vt) · Cs / (Cs + Cd) (1) where Cd is a digit line capacitance and Cs is a memory cell capacitance.

That is, the high-level potential of the memory cell is low from the time of writing, and therefore the data retention period in which the stored information of the memory cell can be recognized as high level at the time of reading becomes short.

Therefore, the word line selection level is set to (Vcc
+ Vt), and a word line boosting circuit for raising the high-level write potential to the memory cell to the power supply potential Vcc level has been provided. The digit line potential Vd at the time of reading at this time is as follows.

Vd = Vcc · Cs / (Cs + Cd) (2) As a result, the data retention period in which the stored information of the memory cell can be recognized as a high level at the time of reading can be lengthened.

FIGS. 4A and 4B are a block diagram showing a general example of a conventional semiconductor memory device having a word line booster circuit and a circuit diagram of a step-down unit included in the word line booster circuit.

In this semiconductor memory device, a plurality of memory cells MC arranged in a matrix of rows and columns, and memory cells of a corresponding row are provided corresponding to each row of the plurality of memory cells and at a selection level. , WLm, and a plurality of memory cells, which are set in a state, and read data of the memory cells in a selected state in the corresponding column are transmitted, and the memory in the selected state , DLn having a plurality of digit lines DL1, DL2, ..., DLn for transmitting data for writing to the cell, and a predetermined one of a plurality of word lines WL1, WL2, ..., WLm according to a row address signal ADr. Of the selected word line, and the selected word line is supplied with a voltage higher than the power supply potential Vcc by a predetermined level according to the boosted signal φRA supplied. X row selection circuit to the selected level
According to the decoder 3, the booster section 21 for generating the boosting signal φRA having a potential higher than the power supply potential Vcc by a predetermined level and supplying the boosting signal φRA to the X decoder 3, and the control signal φRAS4B,
A word line boosting circuit 2 provided with a step-down unit 22 that steps down the level of the boosting signal line transmitting the boosting signal φRA to the ground potential level in synchronization with the timing of setting the word line of the selected level by the X decoder 3 to the non-selection level. , A structure including a Y decoder 4 and a data sense / input / output circuit 5 which select read data from the memory cell array 1, sense-amplify and output the data to the outside, and supply write data to the selected column. There is.

Further, the step-down unit 22 of the word line booster circuit 2
Is an inverter IV3 that receives the control signal φRAS4B at its input end and connects its ground terminal to the ground wire GND1, an inverter IV4 that receives the output signal of this inverter IV3 at its input end and connects its ground terminal to the ground wire GND1, and this inverter IV4. Of the data sensing / input / output circuit 5 is connected to the ground wiring GND1 and the drain thereof is connected to the boosting signal line.
Are usually arranged separately from the ground wiring GND1 so as not to affect data input / output.

A specific layout example of this semiconductor memory device is shown in FIG.

An X decoder 3 is arranged adjacent to the formation region of the memory cell array 1, and a peripheral circuit 7 such as a row control circuit is arranged adjacent to the formation region of the X decoder 3.
A wiring region 8 such as various control signal lines is arranged adjacent to the formation region of the peripheral circuit 7. The word line boosting circuit 2 is arranged adjacent to the wiring region 8 and substantially in the center of the wiring region 8 in the longitudinal direction, and transmits the boosting signal φRA output from the word line boosting circuit 2 by a boosting signal line LφR.
The Ax runs in the wiring region 8 in the longitudinal direction, goes from both ends of the wiring region 8 to both ends of the X decoder 3, and connects both ends to form a closed wiring running on the X decoder 3 in the longitudinal direction. There is. Further, a data sense / input / output circuit 5 is arranged adjacent to the wiring region 8 and the word line boosting circuit 2,
The ground wiring GND2 is arranged separately from the ground wiring GND1.

The boosting signal φR boosted to at least the (Vcc + Vt) level in the boosting section 21 of the word line boosting circuit 2.
A is transmitted to the X decoder 3 through the boosting signal line LφRAx, and the word line selected by the X decoder 3 is (Vcc
+ Vt) boosts to the selected level. As a result, the high-level data write potential of the selected memory cell is
It can be set to the power supply potential Vcc level.

After the writing of data to the selected memory cell and the reading of the stored data are completed, the level of the word line is rapidly changed to the ground potential level by the X decoder 3 and the step-down unit 22 of the word line boosting circuit 2. Wait for the next access.

Since the boosting signal line LφRAx continuously supplies the boosting signal φRA during the dynamic operation period, the wiring width is wider than that of the other signal lines.

[0015]

In this conventional semiconductor memory device, the boosted signal line L.phi.RAx for stepping down the word line of the selected level to the non-selected level of the ground potential level is
Since the voltage is reduced to the ground potential level through the ground wiring GND1 at one location of the voltage reduction unit 22 in the word line booster circuit 2, there is a problem that the ground potential floats and the time required for the voltage reduction increases. Further, since the boosted signal line LφRAx having a wider wiring width than the other signal lines runs in the wiring region 8 from one end to the other in the longitudinal direction, there is a problem that the chip area increases correspondingly.

An object of the present invention is to provide a semiconductor memory device capable of shortening the time required for stepping down the word line and the step-up signal line to the ground potential level and reducing the chip area.

[0017]

A semiconductor memory device of the present invention is provided with a plurality of memory cells arranged in a matrix of rows and columns, provided corresponding to each row of the plurality of memory cells and corresponding to a selection level. A plurality of word lines for selecting the memory cells in the row to be selected, and transmission of read data from the memory cells in the selected state of the corresponding column provided corresponding to each column of the plurality of memory cells. A memory cell array having a plurality of digit lines for transmitting write data to a memory cell, and a predetermined word line among the plurality of word lines is selected according to a row address signal and the selected word line is supplied. A row selection circuit that sets a selection level that is a potential higher than the power supply potential by a predetermined level according to the boosted signal that has been generated, and a row selection circuit from one end to the other end. And a boosting signal line for supplying the boosted signal that is arranged and transmitted to the row selection circuit, and the boosting voltage that is provided close to one end of the row selection circuit and is higher than the power supply potential by a predetermined level. A booster for transmitting a signal to one end of the boosted signal line, and a step-down for stepping down the boosted signal line to the ground potential level in synchronization with the timing of setting the word line of the selection level by the row selection circuit to the non-selection level. And a word line boosting circuit having a section, and the word line of a selected level is connected to the other end of the boosting signal line provided close to the other end of the row selection circuit to select a word line of a non-selection level by the row selection circuit. And a word line step-down circuit for stepping down to the boosted signal line and the ground potential level in synchronization with the timing, and sense amplification of read data from the memory cell array and output to the outside. And a data sense output circuit for controlling the supply to the memory cell array of the data for writing from outside. Also,
The first ground wiring of the first circuit including the word line boosting circuit and the second ground wiring of the data sense / input / output circuit are separately arranged, and the step-down of the boosting signal line by the word line step-down circuit is performed by the first ground wiring. The control signal that changes from the inactive level to the active level in synchronization with the timing when the word line of the selected level is set to the non-selected level by the row selection circuit is used for the step-down section of the word line boosting circuit. A first inverter having an input terminal for receiving a ground terminal connected to the first ground wiring, and a second inverter receiving an output signal of the first inverter for an input terminal and connecting the ground terminal to the first ground wiring. An inverter and a first transistor having a gate receiving an output signal of the second inverter, a drain connected to one end of the boosting signal line, and a source connected to the first ground wiring; A third inverter that receives the control signal at the input end and connects the ground terminal to the first ground wiring; and a word line step-down circuit that receives the output signal of the third inverter at the input end and is grounded. The terminal is the first
A fourth inverter connected to the ground wiring of the second inverter, and a second inverter connecting the output signal of the fourth inverter to the gate and the drain to the other end of the boosting signal line and the source to the second ground wiring. It is configured as a circuit including a transistor.

Further, a second transistor-off means for keeping the second transistor of the word line step-down circuit in the off state is provided during the period in which the predetermined word line is held at the selected level by the row selection circuit, and this second transistor is turned off. The transistor-off means is configured as a circuit including a third transistor having a gate receiving the output signal of the third inverter and a source receiving the output signal of the fourth inverter and a drain connected to the second ground wiring.

[0019]

Embodiments of the present invention will now be described with reference to the drawings.

1A and 1B are a block diagram showing a first embodiment of the present invention and a circuit diagram of a word line step-down circuit thereof, and FIG. 2 is a layout diagram of this embodiment.

This embodiment is shown in FIG. 4 (A), (B) and FIG.
The difference from the conventional semiconductor memory device shown in FIG. 2 is that the word line boosting circuit 2 is arranged close to one end of the X decoder 3, and the boosting signal line LφRA is provided from one end of the X decoder 3 to the other end. Of the word line boosting circuit 2 and the boosting signal φRA from the word line boosting circuit 2 is transmitted to one end of the boosting signal line LφRA, and the inverters IV1 and IV2 and the transistor Tr1 are provided to be close to the other end of the X decoder 3. The word line step-down circuit 6 for stepping down the step-up signal line LφRA to the ground potential level through the ground wiring GND2 is provided in synchronization with the timing of setting the selected level word line to the non-select level according to the control signal φRAS4B. It is in.

The word line step-down circuit 6 has the same circuit configuration as the step-down unit 22 of the word line step-up circuit 2 except that the source of the step-down transistor Tr1 is connected to the ground wiring GND2. And when stepping down the word line,
According to the control signal φRAS4B, the booster signal line LφRA is simultaneously connected to the booster signal line from one end through the ground line GND1 by the step-down unit 22 of the word line booster circuit 2 and from the other end through the word line step-down circuit 6 through the ground line GND2. The configuration is such that LφRA is stepped down to the ground potential level.

That is, since the voltage is stepped down from both ends of the step-up signal line LφRA through the other ground wirings GND1 and GND2, the step-down current is increased and dispersed to reduce floating of the ground potential level, and the step-down time is shortened (for example, 5 ns). You can Further, since it is not necessary to run the boosting signal line having a relatively wide wiring width (for example, about 40 μm) from one end to the other end of the wiring region, the chip area can be reduced accordingly.

FIG. 3 is a circuit diagram of a word line step-down circuit portion according to the second embodiment of the present invention.

The word line step-down circuit 6a of this embodiment is the same as the word line step-down circuit 6 of the first embodiment except that the gate receives the output signal of the inverter IV1 and the source thereof is the inverter I.
A transistor Tr2 for receiving the output signal of V2 and connecting the drain to the ground wiring GND2 is provided.

Ground wiring GN of inverters IV1 and IV2
Since the wiring D1 and the ground wiring GND2 of the transistor Tr1 are separate wirings, when noise exceeding the threshold voltage of the transistor Tr1 is induced in the ground wiring GND2 when the word line is at the selection level, the transistor Tr1 is
1 is turned on to lower the level of the word line, which causes malfunctions such as lowering of the writing level, defective writing, and defective selection.

Therefore, in the word line selecting operation, the transistor Tr2 is always turned on so that the transistor Tr1 is not turned on.

In these embodiments, the source of the step-down transistor Tr1 is connected to the ground wiring GND2 and the voltage is lowered through this, but the source of the transistor Tr1 is connected to the ground wiring GND1 and passed through this. Even if the voltage is lowered, the step-down time can be shortened as compared with the conventional example due to the shorted step-up signal line LφRA and the increased step-down current of the word line step-down circuits 6 and 6a. Further, the increase in the chip area of the word line step-down circuits 6 and 6a is negligible in comparison with the boosted signal line LφRAx arranged in the wiring region 8 of the conventional example.

[0029]

As described above, according to the present invention, the word line boosting circuit is arranged close to one end of the row selecting circuit and the boosting signal is supplied from one end of the boosting signal line on the row selecting circuit. , A word line step-down circuit is provided near the other end of the row selection circuit, and the step-down signal line is stepped down from the other end of the step-up signal line simultaneously with the step-down part of the word line step-up circuit. As the current increases and spreads out,
The floating of the ground potential level is reduced, the step-down time can be shortened, and almost no boosting signal line in the wiring region with a wide wiring width can be eliminated, so the chip area can be reduced accordingly. There is an effect that can be.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention and a circuit diagram of a word line step-down circuit portion thereof.

FIG. 2 is a layout diagram of the embodiment shown in FIG.

FIG. 3 is a circuit diagram of a word line step-down circuit portion according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing an example of a conventional semiconductor memory device and a circuit diagram of a step-down unit of a word line booster circuit thereof.

5 is a layout diagram of the semiconductor memory device shown in FIG. 4. FIG.

[Explanation of symbols]

 1 Memory Cell Array 2 Word Line Boosting Circuit 3 X Decoder 4 Y Decoder 5 Data Sense / I / O Circuit 6, 6a Word Line Stepping Down Circuit 7 Peripheral Circuit 8 Wiring Area 21 Boosting Section 22 Stepping Down Section DL1 to DLn Digit Line GND1, GND2 Grounding Wiring IV1 to IV4 inverters LφRA, LφRAx boosting signal line MC memory cell Tr1 to Tr3 transistor WL1 to WLm word line

Claims (5)

[Claims] 1. A plurality of memory cells arranged in a matrix of rows and columns, and a plurality of memory cells provided corresponding to each row of the plurality of memory cells and having a memory cell of a corresponding row at a selection level in a selected state. The word line and the columns of the plurality of memory cells are provided corresponding to the respective columns, and the read data of the memory cells in the selected state of the corresponding columns are transmitted, and the data for writing to the memory cells in the selected state are transmitted. A memory cell array having a plurality of digit lines, and a predetermined word line of the plurality of word lines is selected according to a row address signal, and the selected word line is supplied with a predetermined level from a power supply potential according to a supplied boosting signal. A row selection circuit having a high potential selection level, and the boosted signal transmitted from the one end to the other end of the row selection circuit are transferred to the row selection circuit. A boosting signal line supplied to the selection circuit,
A booster unit provided near one end of the row selection circuit and transmitting the boosted signal having a potential higher than the power supply potential by a predetermined level to one end of the boosted signal line, and the row selection circuit. A word line boosting circuit having a step-down unit for stepping down the boosted signal line to a ground potential level in synchronization with the timing when the word line at the selected level is set to the non-selected level;
The boosting signal is provided in proximity to the other end of the row selecting circuit and is connected to the other end of the boosting signal line and is synchronized with the timing at which the word line of the selection level is set to the non-selection level by the row selecting circuit. Line and a word line step-down circuit for stepping down to a ground potential level, data for performing sense amplification of read data from the memory cell array and output to the outside, and supply control of external write data to the memory cell array A semiconductor memory device having a sense / input / output circuit. 2. A booster signal line formed by a word line step-down circuit, wherein a first ground line of a first circuit including a word line booster circuit and a second ground line of a data sense / input / output circuit are separately arranged. 2. The semiconductor memory device according to claim 1, wherein the step-down of voltage is performed through the second ground wiring. 3. A step-down portion of a word line boosting circuit is provided with a control signal at an input end thereof which changes from an inactive level to an active level in synchronization with a timing when a row selection circuit sets a word line at a selected level to a non-selected level. A first inverter connecting the receiving ground terminal to the first ground wiring, and a second inverter connecting the receiving ground terminal to the first ground wiring at the input terminal of the output signal of the first inverter,
A word line step-down circuit is provided which is a circuit including a first transistor having a gate receiving an output signal of the second inverter and a drain connected to one end of the boosting signal line and a source connected to the first ground wiring. A third inverter that receives the control signal at an input terminal and connects a ground terminal to the first ground wiring; and a ground terminal that receives an output signal of the third inverter at an input terminal and the first ground wiring. A fourth inverter connected to the fourth inverter; and a second transistor having a gate receiving an output signal of the fourth inverter and a drain connected to the other end of the boosting signal line and a source connected to the second ground wiring. The semiconductor memory device according to claim 2, which is a circuit. 4. A second transistor turning-off means for keeping the second transistor of the word line step-down circuit off during a period in which a predetermined word line is held at the selected level by the row selection circuit. Semiconductor memory device. 5. The second transistor-off means comprises a third transistor
5. The semiconductor memory device according to claim 4, wherein the circuit includes a third transistor which receives the output signal of the inverter in the gate and receives the output signal of the fourth inverter in the source and connects the drain to the second ground wiring.