JPH03250764A - Photoelectric converter - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a photoelectric conversion device, and more particularly to a photoelectric conversion device including a plurality of photoelectric conversion elements capable of accumulating photoelectrically converted charges. INDUSTRIAL APPLICATION This invention is suitably used for the photoelectric conversion apparatus used for the focus detection apparatus of the passive method of a camera, etc., for example.

[Conventional technology] Conventionally, this type of clothing! For example, Japanese Patent Laid-Open No. 1-222583 by the present applicant has already been proposed.

FIG. 14 shows an equivalent circuit diagram of a photoelectric conversion element array disclosed in Japanese Patent Application Laid-Open No. 1-222583.

In Fig. 14, 1-3 to 1-0 are storage type phototransistor arrays (cells), the collectors of which are connected to a common power source, and the control electrode area (base) that stores photoelectrically converted charges. , which has a structure that allows reading from the main electrode region (emitter), and its specific contents are disclosed in, for example, JP-A-62-128678 and JP-A-62-
No. 113468, JP-A-63-24664, JP-A-6
Detailed descriptions are given in No. 3-76476, Japanese Patent Application Laid-Open No. 63-76582, etc. 2-3 to 2-n are PMOS switches for connecting to the power supply and resetting when the base φ7.1 of each bipolar transistor constituting the phototransistor array 1 is applied; 3-1 to 3. , , are NMs connected to each emitter of the bipolar transistor and taken out to the subsequent stage in synchronization with the accumulated signal φ.
OS switches, 4-1 to 4-, are NMOS switches 3
-1 to 3-7 are NMOS switches connected in series to each of them for sending an image signal to the readout line 7. 5-
1 to 5-, are NMOS switches 3-3 to 3-0 and 4-2
Storage capacitance for reading out signals for each pixel connected between each connection point of ~4-, and the ground, 9 sequentially turns on NMOS switches 4-1 to 4-, and reads out image signals one after another. This is a shift register for 8 is an NMOS switch for grounding and initializing the read line 7, to which the output terminals of the NMOS switches 4-1 to 4-, are commonly connected, when signals φ, , r1 are applied; 9 is a read line; an output amplifier for amplifying the image signal outputted to 7, 10-
1 to 10-n are NMOS switches for grounding each emitter of the phototransistor array 1-+"-1□ when φV□ is applied. 107 is a maximum/minimum value detection circuit, which detects the minimum value. It is comprised of circuits 11-1 to 11-n, maximum value detection circuits 12-1 to 12-o, and output amplifiers 13.14.

FIG. 15 shows the configuration of one unit of the minimum value detection circuit.

As shown in FIG. 15, one minimum value detection circuit consists of 1
differential amplifier 3o and one PNP transistor 31
It is composed of The differential amplifier 30 is a constant current circuit 4
11, PMO3) transistors 407, 408, NM
Consists of QS To-17 transistor 4o9°410. P
The emitter line of the NP transistor 31 is fed back to the inverting input (1,) of the differential amplifier 3o, and is fed back to the non-inverting input (1,
) includes phototransistor arrays 1-+ to 1. Each emitter of each pixel column is input. The level of the non-inverting input of the differential amplifier 3° (r-+) is the level of the inverting input (I, 1
g), the PNP transistor 3I
By displacing the base potential of PN to almost the power supply voltage level,
Turn off the P-type transistor 31. Therefore the 14th
No voltage is generated at the input of the output amplifier 13 shown in the figure. The output voltage is generated in the PNP transistor 31 when the lowest voltage is applied to the non-inverting input (In,) of the differential amplifier 30, and the minimum value is detected.

FIG. 16 shows the configuration of one unit of the maximum value detection circuit.

As shown in FIG. 16, one maximum value detection circuit consists of 1
differential amplifier 32 and one NPN transistor 33
It is composed of The differential amplifier 32 is connected to the constant current circuit 4
01, PMO3l-transistor 4.02,403, NM
QS consists of transistors 404 and 405. The emitter line of the NPN transistor 33 is connected to the differential amplifier 32.
It is fed back to the inverting input (In2) of , and serves as an output line. Each emitter of each pixel column is connected to the non-inverting input (1,,). Non-inverting input of differential amplifier 32 (I□
) is lower than the inverting input (1, ), the base potential of the NPN transistor 33 is lowered to approximately the voltage level of the negative power supply, and the NPN transistor 33 is turned off. The NPN transistor 33 generates an output voltage when the highest voltage is applied to the non-inverting input of the differential amplifier 32, and the maximum value is detected.

In addition, R is the minimum value detection circuit and the maximum value detection circuit,
Both indicate load resistance.

FIG. 17 is a timing chart illustrating the operation of the photoelectric conversion element array shown in FIG. 14.

First, a reset is performed. At time t1-t21-l, φ and □ are set to low level, and PMOS switch 2-1
By turning on ~l, the bases of the phototransistor arrays (hereinafter referred to as two pixel columns) 1-1 to 1- are turned on. It is fixed at the potential of

Next, by setting φvrs and φ to high level (ON) during the time period t to t4, the NMOS switches 10-+ to 10-n and 3-1 to 3-n become conductive.
Storage capacitors 5-1 to 5-0 are grounded and residual charges are reset. When the reset of each of the base and emitter of the pixel columns 1-1 to l-0 is completed, the storage operation starts next.

When the storage operation begins, the photoelectrically converted charges are transferred to pixel column 1-1.
~1-, , is accumulated in the base region. At this time, the base and emitter of the pixel column are floating (capacitively loaded state), and a voltage reflecting the base potential is generated at the emitter.

When reading signals sequentially, NMOS switch 4-
1 to 4-7 are turned ON sequentially by the shift register 6,
Storage capacity 5-1~5~. The signal charge accumulated in the signal charge is read out to the readout line 7. Each time the shift register 6 is inputted, the NMOS switches 4-1 to 4-4 are sequentially selected. Immediately before selecting the NMOS switches 4-1 to 4-, φ1. to turn on the NMOS switch 8,
Residual charges on the readout line 7 are reset.

Japanese Patent Application No. 63-47644 discloses that the 18th
By configuring a photoelectric conversion device as shown in the figure and FIG.
A method of D conversion has been proposed.

In these devices, the difference between the maximum and minimum accumulation levels of the photoelectric conversion element array is used as a reference level (1) to determine whether or not accumulation has been performed to an appropriate level. ．． This is done depending on whether the target is reached or not. 102 is V a m x
103 is a differential amplifier for taking the difference between V a + n and V a + n, and 103 compares the output of the differential amplifier 102 with a predetermined reference level ■, r, and determines that an appropriate accumulation level has been reached. The signal φ of the comparator 103 is a comparator. . , p are inverted, the microcomputer 104 detects that the storage has been carried out to the reference level, and sends a pulse φ, to the photoelectric conversion element array 101 to end the storage. At the same time, a signal SN is sent to the storage circuit 105 to store the V mil level at the end of accumulation. Next, read pulses φ and φnrm are sent, and an image (video) signal is read out from the photoelectric conversion element and A/D converted.

In the example shown in Fig. 18, the level of the A/D conversion range is shifted according to the range of the image signal, and the
In the illustrated example, the pixel signal is level-shifted in accordance with the A/D conversion range, so that A/D conversion is performed between the maximum and minimum values of the image signal.

Based on the digitized pixel signals obtained in this way,
Focus determination can be performed by performing calculations disclosed in Japanese Patent Application Laid-open No. 7313, Japanese Patent Application Laid-open No. 101513-1982, or Japanese Patent Application Laid-Open No. 18314-1983.

However, in the conventional photoelectric conversion device described above, the image signal and the maximum and minimum values of the accumulated signal of the photoelectric conversion element array are outputted through different readout circuits, so differences in readout gain and mismatch between amplifiers 9, 13 and 14 may occur. This may cause the actual maximum or minimum value of the pixel signal to differ from v, 8 or V.
The value of 1n may deviate, and if the accumulated charge is controlled based on the difference between Department is A
/D conversion range was sometimes exceeded.

Note that the difference in read gain occurs as follows.

For example, in FIG. 14, the capacity of storage capacitor 5 is CTl,
If the parasitic capacitance of the readout line 7 is CH, then the emitter potential of the phototransistor 1-1, 1, is the readout line 7.
When read out, there is no output CTI+CH.

On the other hand, since the V III l n and V wan outputs are read out with a gain of 1, a shift occurs.

In order to solve this problem, the applicant has filed a patent application
The photoelectric conversion device described in No.-301818 was proposed.

[Problems to be Solved by the Invention] However, the above-mentioned Japanese Patent Application No. 1-301818 has the following problems, and improvements have been desired.

In other words, in a configuration that detects the maximum and minimum values and outputs them on the same line as the image signal, there is a bus from the light receiving element to the common output line via the readout circuit, and a bus from the maximum/minimum value detection circuit to the common output line. The balance with the bus leading to is good (
If this cannot be achieved, the SN ratio will decrease and the signal will have large variations from bit to bit. In this case, it is not enough to simply improve the quality of the image signal itself; it is also necessary to accurately detect the maximum value/minimum value data for determining the accumulation time of the light receiving element, and furthermore, it is necessary to accurately detect the detected maximum value/minimum value data. The minimum value data must be output to the common output line without adding noise components.

In addition, particularly recently, in a photoelectric conversion device for photometry, a configuration in which a photoelectric conversion element array is arranged two-dimensionally has been desired in order to perform sensing of a subject in the vertical and horizontal directions.

A conceivable configuration for this purpose is to arrange chips of a plurality of photoelectric conversion devices vertically and horizontally. However, if such a configuration is adopted, not only the manufacturing cost increases, but also a signal with a small signal-to-noise ratio may be obtained depending on the combination.

In particular, if a digital circuit that generates a clock signal, etc. for driving a corresponding photoelectric conversion element array is placed near the light receiving element array of another photoelectric conversion element array, the SN
A significant decrease in the ratio was observed.

This is thought to be due to noise components from the digital circuit getting mixed into the photoelectric conversion signal, which is considered to be a major factor.

Furthermore, among the plurality of photoelectric conversion element arrays, in the array located on the edge side of the chip, the light receiving element array should be on the inside and the readout circuit section should be on the outside. The light receiving section is influenced by the array inside the adjacent chip, making it impossible to read signals accurately.

[Problems to Solve the Problems] Therefore, the present inventors have developed a light receiving element array section, a reading circuit section,
Combining multiple digital circuit sections, analog signal processing sections, etc. to find the configuration that produces the lowest noise (larger signal), and then integrating parts of them and placing them at predetermined positions on the semiconductor chip. By doing so, we aimed to further reduce some noise.

A configuration for solving the above-mentioned technical problem includes a light receiving element array section having a plurality of light receiving elements capable of accumulating photoelectrically converted charges, and a structure for reading out a signal based on the photoelectrically converted charges in the light receiving element array section. A photoelectric conversion device in which a plurality of photoelectric conversion element arrays arranged in a substantially planar manner are arranged two-dimensionally on the same substrate; Among the photoelectric conversion element arrays located on the edge side of the substrate, the readout circuit of the photoelectric conversion element array faces inside the substrate, and the light receiving element array portion of the photoelectric conversion element array faces outside of the substrate. (This is a photoelectric conversion device characterized by being arranged as follows.

[Example] Embodiments of the present invention will be described in detail below with reference to the drawings.

(Description of Structure of Photoelectric Conversion Device) FIG. 1 is a schematic top view for explaining the structure of a photoelectric conversion device according to the present invention.

1001.1101.2001.2101.3001.
3101.4001゜4101 Light receiving element array in photoelectric conversion element array, 1002.1102.2002.
2102.3002.3102.4002.4102 is a readout circuit section of the photoelectric conversion element array. One of these photodetector arrays and one of the readout circuit sections constitute one of the photoelectric conversion element arrays. The readout circuit section is composed of an NMOS switch, a storage capacitor, a maximum value detector, a minimum value detector, etc., as will be described later. Then, the photoelectric conversion element array is attached to the semiconductor chip in two directions in the horizontal direction in the figure.
A plurality of photoelectric conversion element arrays (eight in this case) are arranged, with lines arranged in three rows above and below, and two lines arranged in a direction intersecting the lines in one row. Light receiving part 1001.110
1 and 3001.3101 are arranged at the end of the chip, and the corresponding readout circuit parts 1002.1102 and 3002.3102 are arranged toward the inside of the chip. In the array, light from the edges is prevented from entering the readout circuit and causing malfunction.

Further, two photoelectric conversion element arrays including 1002 and 1102 are connected by a readout line 5010 and a line 50
Analog signal processing circuit section 5 through 09 and 5015
A signal is output to 002.

Similarly, the photoelectric conversion element array including 3002 and 3102 is connected by a line 5017, and a line 5016 and a switch 5
021 to line 5015.

The photoelectric conversion element array including 2012.2102 is connected by line 5012.5014 and connected to line 5015 via switch 5020.

Similarly, the photoelectric conversion element array including 4002.4102 is connected to the switch 5020 by the line 5011.5013.
is connected to line 5015 via.

In this way, the readout line is set as a common line via the switch with reference to 5015, and the light receiving element array 4001.
4101.2001.2101 and reaches the analog signal processing circuit section 5002 through approximately the center of the chip. The digital circuit section and analog signal processing circuit section, which generate clocks for driving each photoelectric conversion element array and serve as Ilo, are placed together at a predetermined location on the edge of the chip, and the generated noise is removed from the readout line. This prevents any negative impact on the

5003.5004.5005.5006 are comparators that control the accumulation time, and 5003 is 10
02.1102, and 5004 corresponds to 4002.
4102, 5005 is 2002.210
2, and 5006 corresponds to 3002.3102.

Moreover, 5007 and 5008 are pad portions having a plurality of pads for electrical connection with the outside of the chip.

(Schematic Description of Photoelectric Conversion Element Array) FIG. 2 is a circuit diagram showing one configuration of a photoelectric conversion element array, which is a characteristic part of the photoelectric conversion device of the present invention. Here, one of the eight photoelectric conversion element arrays shown in FIG. 1 will be explained as an example.

Components that are the same as those shown in FIG. 14 are designated by the same reference numerals and their explanations will be omitted.

As shown in the figure, the photoelectric conversion element array according to the present invention is provided with the following structural members in addition to the conventional photoelectric conversion element array shown in FIG. 17 and 18 are NMOS connected to the outputs of the maximum value detection circuits 12-1 to 12-0 and the minimum value detection circuits 11-1 to 11-1, respectively, for extracting the maximum value and minimum value to the subsequent stage in synchronization with φ. switch, 1.9.20 is NMOS switch 17.18
NMOS switches 15 and 16 are connected in series to send the maximum value and minimum value to the output line 7, respectively.
MOS switch 17.18 and NMOS switch 19.
This is a storage capacitor connected between each of the 20 connection points and the ground for reading out the maximum value and minimum value signals.

FIG. 3 is a timing chart illustrating the operation of the photoelectric conversion element array.

Note that the operation up to the start of accumulation is the same as that of the conventional photoelectric conversion element array described using FIGS. 14 to 17, and therefore a description thereof will be omitted.

When the storage operation starts, the photoelectrically converted charges are transferred to pixel columns 1-3.
~1-, is accumulated in the control electrode region (base). At this time, the bases and emitters of the pixel columns 1-5 to 1-11 are floating (capacitively loaded state), and a voltage reflecting the base potential is generated at the emitters. In addition, an output corresponding to the maximum output of pixel rows 1-+ to 11 appears in V, □,
(2), 1, pixel rows 1-1 to 1. The output corresponding to the minimum output appears.

At the end of the accumulation, the maximum output level, the minimum output level, and the output level of each pixel at that time are accumulated in the storage capacitors 15, 16 degrees 5-1 to 5-, respectively, by the transfer pulse φ. When reading, the NMOS switch 19
,20. t, ~, l, l are sequentially turned on by the shift register 6, and storage capacitances 15.16.5-, ~5-
．． The signal accumulated in the readout line 7 is read out to the readout line 7. The shift register 6 switches NMOS switches 19 degrees 20.4-+ to 4- . ．． Select sequentially.

Immediately before selecting the NMOS switches 19, 20.4-, ~4-0, the NMOS switch 8 is turned off by φ, , r.
The charge remaining in the read line 7 is reset to the N state.

As is clear from the above, in this embodiment, the readout gain is increased until the signals of the maximum output and the minimum output of the photoelectric conversion element array at the end of accumulation can be read out to the same readout line through the same readout circuit as each pixel. Therefore, the maximum output and minimum output of the photoelectric conversion element array can be obtained more accurately without being affected by amplifier mismatch.

FIGS. 4 and 5 are block diagrams of specific photoelectric conversion devices using this embodiment.

4 and 5, 101 is the photoelectric conversion element array shown in FIG. 2, 102 is V, 0. A differential amplifier 103 for taking the difference between the output of the differential amplifier 102 and a predetermined reference level 1. ．． a comparator 109 for determining whether an appropriate accumulation level has been reached by comparing the
and 111 are storage circuits that respectively store the minimum value and maximum value signals output from the Video line, and 110 is a differential circuit that takes the difference between the output of the recording circuit 109 and the output signal of the photoelectric conversion element array output from the Video line. amplifier, 1
12 is a differential amplifier that takes the difference between the outputs of the recording circuit 111 and the recording circuit 109, and 104 is a microcomputer. The microcomputer includes a CPU core 104a,
It is composed of a ROM 104b, a RAM 104c, and an A/D converter 104d.

In the photoelectric conversion device shown in FIG. 4, first, the microcomputer 104 sends a reset signal φ716. φvr
, and start accumulation. Next, the inverted signal φ of the comparator 103. . In response to Il, , φ is output and storage is stopped. Further, φnrg and φ are output and read out. At this time, the sampling signal SH is sent from the microcomputer 104 to the storage circuit 109 at the timing of outputting the minimum value, and the minimum value is stored. The output of the photoelectric conversion element array that is subsequently output is sent to the differential amplifier 110.
A/D conversion is performed by taking the difference from the minimum value. At this time, the reference potential Vr+ for reference of A/D conversion is the ground potential,
Since V rn is set to V tar, A/D conversion is performed between approximately the maximum value and the minimum value of the output of the photoelectric conversion element array. is read out more accurately than in the conventional photoelectric conversion device shown in FIG. 11, so A/D conversion is performed accurately on the contrast portion of the object.

In the photoelectric conversion device shown in FIG.
) 12 respectively and store the maximum value and minimum value of the photoelectric conversion element array in the storage circuit 111.1.09, respectively. The output of the photoelectric conversion element array, which is subsequently outputted, is input to the A/D converter in a form in which the difference from the minimum value is calculated by the differential amplifier 110. At this time, the reference potential V for A/D conversion
r+ is the ground potential, and ■rn is the difference between the maximum value and minimum value obtained by the differential amplifier 112. V Il
l I n and ■11. As mentioned above, the values of V do not necessarily accurately reflect the maximum and minimum values of the actual photoelectric conversion element array, so V IIIm V +a+n is
Even if the accumulation ends when the r e t level is reached, the actual signal width is not necessarily V raf. Therefore, by setting the actual signal width as the A/D conversion range as in the example of the photoelectric conversion device shown in Fig. 4, the A/D conversion range can be effectively used without exceeding the A/D conversion range. Conversion can be performed.

FIG. 6 is a circuit diagram showing the configuration of a second embodiment of a photoelectric conversion element array, which is a characteristic part of the photoelectric conversion device of the present invention.

Note that the same reference numerals are given to the same constituent members as those shown in FIG. 2, and the explanation thereof will be omitted.

The feature of this embodiment is that a differential amplifier 26 is used in addition to the maximum and minimum values of the output of the photoelectric conversion element array, and the difference between these is taken and read out from the same readout line as the photoelectric conversion element array. It's right there. The operation is almost the same as in the first embodiment. Instead of the maximum value of the output of the photoelectric conversion element array, the difference between the maximum value and the minimum value is stored in the storage capacitor 21 by φ, and N is stored by the shift register 6.
The difference is that it is read out to the readout line 7 through the MOS switch 23.

In this case, by adopting a configuration as shown in the photoelectric conversion device of FIG. 7, the same effect as the example shown in the photoelectric conversion device of FIG. 5 can be obtained. That is, the microcomputer outputs the sampling pulse SHI at the timing when the difference between the maximum value and the minimum value read from the Video line and the minimum value are output.
and SH2, respectively, and each signal is stored in the memory circuit 113 and the memory circuit 109. The output of the memory circuit 113 is A
The output of the photoelectric conversion element array, which serves as a reference potential on the high-potential side during /D conversion and is subsequently outputted, is sent to the differential amplifier 110.
A/D conversion is performed by taking the difference from the output of the memory circuit 109.

In this example, we have given an example of reading out the difference between the maximum value and the minimum value of the accumulated signal of the photoelectric conversion element array. The same readout system may be used to read out the difference from the bit (for example, a light-shielded bit). Further, depending on the necessity of processing at a subsequent stage, the data may be read not only by the difference but also by addition, multiplication by a constant, etc.

As explained above, the gap between the signal obtained from the maximum value detection means and/or the minimum value detection means and the accumulated signal of the photoelectric conversion element is eliminated, and the charges accumulated in the plurality of photoelectric conversion elements are accurately reflected. You can get the signal.

Further, according to the photoelectric conversion device of the present invention, there is no deviation between the signal calculated based on the signal obtained from the maximum value detection means and/or the minimum value detection means and the accumulated signal of the photoelectric conversion element. , it is possible to obtain a signal that accurately reflects the charges accumulated in a plurality of photoelectric conversion elements.

(Schematic Description of Structure of Photoelectric Conversion Element) FIG. 8 is a schematic plan view showing the structure of the photoelectric conversion element in the photoelectric conversion device according to the present invention. Here, one bit of the photoelectric conversion element array will be explained.

FIG. 8 is a block diagram of one bit of the photoelectric conversion element of the present invention.

202 is a bipolar transistor of a light receiving element that becomes a sensor, and 201 is a PMO for resetting its base.
3) The transistor 203 is an NMOS transistor whose emitter is connected to a predetermined potential and whose base is used to reset the potential due to the photogenerated carriers accumulated. These three transistors perform optical signal storage and reset.

204 is an amplifier used for detecting the maximum value when a plurality of 1-bit blocks are arranged; 205 is an amplifier used for detecting the minimum value; for example, the amplifier 205 is used for detecting the minimum value. This is an amplifier as shown in FIGS. 15 and 16. The signals generated by the light receiving element pass through these amplifiers, and the maximum and minimum values are detected, respectively.

206 and 207 are NMO3 transistors for signal transfer, 208 and 209 are capacitive loads for storing the signals, 210 and 211 are NMO3 transistors for sequentially reading out the signal loads stored in the capacitive loads, and 212
is a shift register for sequentially scanning the NMO3l-transistor for reading.

Here, MO3 for signal transfer, capacitive load, MO for reading
3 are connected two each, of which 20
7,209,21.1 is for dark noise correction, 206,2
08 and 21.1 are used for optical signal accumulation, and are output as N output and S output, respectively, and are then used to correct dark noise through a differential amplifier or the like.

(Description of Layer Structure of Photoelectric Conversion Element) FIGS. 9(A) and 9(B) are schematic cross-sectional views in the AA′ll+ direction of 1 bit of the above-mentioned photoelectric conversion element, respectively. In Fig. 9 (A), from the right, PMO3 for base reset, bipolar transistor for light reception that performs photoelectric conversion, NMO3 for resetting the emitter, amplifier for minimum value detection, amplifier for minimum value detection, and NMO for signal transfer.
3. A signal storage capacity is provided.

Further to the left, a signal storage capacitor, a readout NMO 3, and a scanning shift register are successively arranged from the middle cloth in FIG. 9(B).

Here, for the sake of convenience, the cross-sectional view of the photoelectric conversion element is divided into two parts so as not to complicate the drawings and explanation.

In FIG. 9(A) and FIG. 9(B), 301 is a P-type semiconductor substrate, 302 is a P-buried layer containing P-type impurities, 303 is an N-buried layer containing N-type impurities, 304 is an N-epitaxial layer (N-ep) containing N-type impurities.
i), 305 is a P- region containing a trace amount of P-type impurity,
306 is an N0 region for lowering the collector resistance, 307 is a collector electrode made of bosilicon, and 308 is an ohmic contact layer for electrically connecting the collector electrode 307 and the N° region 309. In the P- region, which becomes the base region of the light-receiving bipolar transistor,
It is connected to an A° C. wiring 331 via a P′ region 310 containing P-type impurities. 31 is an N3 region containing N-type impurities and serving as an emitter, and is connected to the wiring via polysilicon. PMO3 for base reset consists of a P' region 312-1 connected to a P- region 309 which becomes a source, polysilicon which becomes a base electrode provided via an insulating film 336, and a P+ region 3 which becomes a drain.
It is composed of 12 to 2. Reference numeral 337 denotes an element isolation region containing an N-type impurity, and is electrically connected to the N' region 306. NMO5P- for emitter reset
It is formed of N'' regions 315 and 316 formed in the region 305 and a gate electrode 317 made of polysilicon placed through an insulating layer. 318 is a channel stopper containing P-type impurities. 319 is a maximum value detection amplifier, and 320 is a minimum value detection amplifier.

The signal transfer NMO3 is an NMO formed in the P- region 321.
It is composed of zero regions 322 and 323 and a gate electrode 324 made of polysilicon placed through an insulating layer.

325 is a P-type region containing P-type impurities and serving as a channel stopper. The storage capacitor is formed by the P- region 321 and the polysilicon electrode 327 arranged through the insulating layer 336, and the readout NMO 5 is formed by the N4 regions 328, 329 formed in the P- region and the The gate electrode 330 is made of polysilicon and is arranged in the same manner as shown in FIG. 338 is a P-type region containing a P-type impurity and serving as a channel stopper.

An insulating layer 332 is provided between each electrode 331, and the wiring 411331 and the insulating layer 332 are further covered with an insulating layer 333. Reference numeral 334 denotes a light-shielding layer, which is a one-layer region provided to prevent unnecessary light from being irradiated to unnecessary parts (particularly regions other than a part of the sensor). A window is formed in the light shielding layer 334 corresponding to the light receiving part of the sensor.

335 is an insulating layer provided on the surface of the photoelectric conversion element as a protective layer.

(Explanation of additional configuration of photoelectric conversion element array) Also, among the eight photoelectric conversion element arrays, 10011002.2001,
2002, 3001, 3002, 4001.4002 includes, in addition to the above-mentioned photoelectric conversion element bits for reading optical information, bits for reading dark components, bits for maximum value detection, and bits for minimum value detection, as shown in Figure 10. Dummy bits are provided on the array.

Also, 11 out of 8 photoelectric conversion element arrays. OL.

1102.2] Old, 2102, 3101, 3102, 4
101.4102, in addition to the above-mentioned photoelectric conversion element bits for reading out optical information, there are also bits for reading dark components, bits for maximum value detection, bits for minimum value detection, and dummy bits on the array as shown in Figure 11. It is set in.

FIG. 10 shows 100 of the photoelectric conversion element arrays of the present invention.
1.1002,2001,2002,3001,300
This shows the configuration of 2.4001.4002. 6
01 is a p-ch MOS transistor for base reset, 602 is a bipolar transistor that performs photoelectric conversion as a light receiving element, and 603 is an n-C for emitter reset.
h MOS transistor, 604 is maximum value detection circuit, 6
05 is the minimum value detection circuit, 606 is the n-ch for signal transfer
MOS transistor 607 is a capacitive load for storing signal charges, 608 is an n-ch MOS transistor for sequentially reading out the charges stored in the storage capacitor, and 609 is a shift register for scanning MO3 for reading.

Each block 606, 607, and 608 consists of two components, an N component for noise correction and an S component for signal accumulation, as shown in FIG.

The light-receiving element 602 undergoes an appropriate reset operation by the MOS transistors 601 and 603, and then begins to accumulate optical signals, and stores the charges generated in response to the irradiated light through the MOS transistors 606 and 607. can be stored in a capacity of When the accumulation is completed, the shift register 609
starts scanning, and the charge stored in 607 is M of 608.
The signals are output sequentially via the OS transistors. During this time,
The maximum value and minimum value detection circuits 604 and 605 detect and output the maximum value and minimum value from among the plurality of arranged pixels.

In addition to effective pixels for reading out optical information, this photoelectric conversion element array is provided with dark pixels for reading out dark components, minimum value detection bits, maximum value detection bits, and dummy pixels. Among these pixels, the dark pixel is used to read out the dark output which is a reference for the optical signal output of all pixels, and the light receiving element is shielded from light. The minimum value and maximum value detection bits are the maximum values detected in 604 and 605.

This is to read the minimum value using the same readout path as the effective pixel, and the maximum and minimum value output lines are used for transfer 1i103
It is connected to the storage capacitor 607 via 606 . This effect is described in detail in Japanese Patent Application No. 1-301818. The maximum value and minimum value detection bits have no relation to the output of the light receiving element due to the above-mentioned configuration, but 601. , 602, 603 and reset MO3 transistors are arranged in the same manner as other pixels. Further, dummy pixels are arranged around the effective pixels to eliminate external influences on the effective pixels.

FIG. 11 shows 11 of the photoelectric conversion element arrays of the present invention.
．． 01,1102,21012102,3101,31
02,4101. ．． 4102 shows the configuration of 4102. 501 is p-ch MOS for base reset)
502 is a bipolar transistor that performs photoelectric conversion as a light receiving element, 503 is an n-ch MOS transistor for emitter reset, 504 is a maximum value detection circuit, 505 is a minimum value detection circuit, and 506 is an n-channel transistor for signal transfer.
507 is a capacitive load 2508 is an n-ch MOS transistor for sequentially reading out the charges stored in the storage capacitor, 50
9 is a shift register for scanning MO3 for reading. In each block 506, 507, 508, the 8th
As shown in the figure, it consists of two components: an N component for noise correction and an S component for signal accumulation. Light receiving element 502
After an appropriate reset operation is performed by the MOS transistors 501 and 503, the optical signal begins to accumulate.
The charges generated in response to the irradiated light are transferred to 506 MOS
) - stored in a capacity of 507 via transistors. When the accumulation is completed, the shift register 509 starts scanning,
The charges stored in 507 are sequentially outputted through MOS transistors 508. During this time, the maximum value and minimum value detection circuits of 504° and 505 detect and output the maximum value and minimum value from among the plurality of arranged pixels.

Further, in addition to the effective pixels for reading optical information, the present photoelectric conversion element array is provided with dummy pixels. Since this array is used bare with the array shown in FIG. 10, dark pixels and maximum value and minimum value detection bits are not added.

(Description of manufacturing method) Figures 12 (A) to (E) and Figures 13 (A) to (E) are
1 is a flowchart of an embodiment of a method for manufacturing a photoelectric conversion element array of the present invention. A method for manufacturing a photoelectric conversion element array according to the present invention will be described below using these drawings.

In addition, Fig. 12 (A) to (E), Fig. 13 (A) to (E)
) indicate the manufacturing method for 1 bit of the photoelectric conversion element shown in FIGS. 9(A) and 9(B), respectively, so they are given the same reference numerals as in FIGS. 9(A) and 9(B). do.

In the present invention, it is necessary to form a bipolar NPN transistor as a light receiving element, a MOS FET as a transfer reset transistor, a maximum value/minimum value detection circuit, an analog signal processing circuit, a digital circuit, etc. on the same chip. Therefore, each element is monolithically integrated on a Si substrate using a so-called B1-CMOS process technology.

First, as shown in FIGS. 12(A) and 13(A), N-type and P-type buried layers 303 and 302 are formed on a P-type St substrate 301 using ion implantation and diffusion techniques. . As is used as an impurity in the N-type buried layer, and B is used in the P-type buried layer.

Next, as shown in FIGS. 12(B) and 13(B), an N-type epitaxial layer 3 is formed by epitaxial growth technology.
04 and P- (P well) by ion implantation of B.
An N4 region 306 is formed in the region 305 by P ion implantation. This N4 region 306 is formed mainly to reduce the collector resistance of the NPN l-transistor. Next, a field insulating film layer 336 is formed by selective oxidation. Thereafter, a P region 318 is formed by B ion implantation, and an N region 337 is formed by P ion implantation.

This is generally called a channel stop, and is intended to prevent parasitic transistors from being formed in isolation regions between elements. Next, Figure 12 (C) and Figure 13 (
As shown in C), a P-type region 309 is formed by ion-implanting B. This is used as the base of the NPN transistor and also used as the light receiving part of the sensor.

Next, as shown in FIG. 12 (D) and FIG. 13 (Dl), polysilicon is deposited and buttered to form NPs.
An emitter electrode of the N transistor and a gate electrode 313 of the MOS transistor are formed.

This polysilicon electrode is also used as a diffusion source for N-type diffusion, and is also used as a contact for the collector electrode 307 of the NPN transistor using P as an impurity. Next, by ion-implanting As, the N-type region 315,
318 and P-type region 31 by ion-implanting B.
0,312-1,312-2 is formed. N-type region 31
5.318 is the source of the n-ch MOS transistor.
Used as a drain region. Also, the P-type region 309,3
10.312-2 is used as the source/drain region of the p-ah MOS transistor. The P-type region 310 is also used as a contact for the base electrode of an NPN transistor.

Next, as shown in FIG. 12(E) and FIG. 13(E), an insulating film 332 is deposited, a contact hole is formed by buttering, and 82 is further deposited and buttered.
Aβ distribution is achieved by etching! [Form 331. This is used for interconnection between each element. Next, an insulating film 333 is further deposited, Aρ is deposited on top of the insulating film 333, and by buttering and etching, Al
1. A region 334 is formed. This is mainly used as a light-shielding film to prevent light from hitting areas other than the sensor's light-receiving area. Although not shown in this figure, the insulating film 33
A contact hole is formed in 3 to make it conductive to the /l wiring in the lower layer, and the first layer 334 used as the light shielding film is connected to the second layer 334.
It can also be a J2 wiring layer. Thereafter, PSG (phosphorus glass), 5iN (silicon nitride film), etc. are formed as a protection film on the top, and the whole process is completed.

Although not mentioned in the above description, the polysilicon layer is also used as wiring between elements or as a capacitor electrode.

Further, high resistance regions such as the P-type head regions 305 and 321 are often used as resistors in analog processing circuits and the like.

Note that only the portion of the light-shielding film at A° C. that defines the aperture of the light-receiving element, which largely depends on the photoelectric conversion operation, is shown;
A using the same process to similarly shield other circuits.
A ρ film may be formed, or a light-shielding film made of an organic material or an inorganic material may be further provided on a desired portion of the upper insulating film. In addition to the effects, it also has the following effects.

In other words, the signal output lines from each photoelectric conversion element array are connected via switches to the common signal line that is routed through the gap that forms the cross section of the four central arrays. The signal output line and the common signal line can be shortened to reduce the probability of noise being introduced, and the LCR constant can be made small to prevent signal delay and SN ratio deterioration.

[Effects of the Invention] According to the present invention, among a plurality of photoelectric conversion element arrays that are two-dimensionally monolithically arranged, those located on the edge side of the substrate are arranged such that the photoelectric conversion element array is placed on the edge side of the substrate and the photoelectric conversion element array is placed on the inside side of the substrate. By monolithically arranging it in a direction that serves as a readout circuit, the following effects can be achieved.

(1) Compared to the case where a readout circuit is placed on the outside and a light receiving element is placed on the inside, which is the reverse arrangement of the present invention, the interaction with the photoelectric conversion element located further inside the substrate (for example, crosstalk and stray light Malfunctions due to components are almost no longer observed.

In addition, the common line for output signals from each photoelectric conversion element array is shortened, reducing signal delay and reduction in S/N ratio.

(2) Even if the arrangement of the light-receiving element array is determined for distance measurement, the readout circuits are arranged densely, so the area of the semiconductor substrate is reduced and the manufacturing cost is reduced.

(3) The light-shielding layer of the readout circuit in the photoelectric conversion element array located at the edge of the substrate can be formed integrally with the light-shielding layer of the photoelectric conversion element array located inside, increasing design freedom and reducing manufacturing costs. The result was also reflected in the results.

[Brief explanation of drawings]

FIG. 1 is a schematic top view showing the configuration and arrangement of a photoelectric conversion device of the present invention. FIG. 2 is a circuit diagram showing the configuration of a first embodiment of a photoelectric conversion element array, which is a characteristic part of the photoelectric conversion device of the present invention. FIG. 3 is a timing chart illustrating the operation of the photoelectric conversion element of the first embodiment. Figures 4 and 5 are
FIG. 2 is a block diagram of a specific photoelectric conversion device using the photoelectric conversion element array of the first embodiment. FIG. 6 is a circuit diagram showing the configuration of a second embodiment of a photoelectric conversion element array, which is a characteristic part of the photoelectric conversion device of the present invention. FIG. 7 is a block diagram of a specific photoelectric conversion device using the photoelectric conversion element array of the second embodiment. FIG. 8 is a schematic block diagram for one bit showing the configuration of a photoelectric conversion element in a photoelectric conversion device according to the present invention. FIGS. 9(A) and 9(B) are schematic cross-sectional views of a 1-bit photoelectric conversion element in a photoelectric conversion device according to the present invention. FIG. 10 is a schematic plan view showing a first configuration of a photoelectric conversion array in a photoelectric conversion device of the present invention. FIG. 11 is a schematic plan view showing a second configuration of the photoelectric conversion array in the photoelectric conversion device of the present invention. Figures 12 (A) to (E) and Figures 13 (A) to (E)
1 is a flowchart of a method for manufacturing a photoelectric conversion array in a photoelectric conversion device according to the present invention. FIG. 14 is an equivalent circuit diagram of a photoelectric conversion element array shown in Japanese Patent Application No. 63-47644. FIG. 15 is a circuit diagram showing the configuration of one unit of the minimum value detection circuit. FIG. 16 is a circuit diagram showing the configuration of one unit of the maximum value detection circuit. FIG. 17 is a timing chart illustrating the operation of the photoelectric conversion element array shown in FIG. 14. FIGS. 18 and 19 are block diagrams of specific photoelectric conversion devices using conventional photoelectric conversion element arrays.

Claims (5)

[Claims] (1) A light-receiving element array section having a plurality of light-receiving elements capable of accumulating photoelectrically converted charges, and a readout circuit section for reading out a signal based on the photoelectrically converted charges in the light-receiving element array section are substantially A photoelectric conversion device in which a plurality of photoelectric conversion element arrays arranged in a plane are two-dimensionally arranged on the same substrate, wherein one of the plurality of photoelectric conversion element arrays is located on an end side of the substrate. The photoelectric conversion element array is arranged such that the readout circuit of the photoelectric conversion element array faces inside the substrate and the light receiving element array portion of the photoelectric conversion element array faces outside the substrate. Features of photoelectric conversion device. (2) Some of the plurality of photoelectric conversion element arrays are arranged on both end sides of the substrate, and the remaining parts are arranged so that the arrangement direction of the light receiving element arrays intersects between them. The photoelectric conversion device according to claim 1. (3) The readout circuit includes storage means for storing signals based on photoelectrically converted signal charges and transfer means for transferring the signals stored in the storage means to a common output line. The photoelectric conversion device according to claim 1. (4) The photoelectric conversion according to claim 1, wherein the readout circuit includes a detection circuit that detects at least one of a maximum value and a minimum value of charges accumulated in the light receiving element array section. Device. (5) The photoelectric conversion device according to claim 1, wherein the charge accumulation region of the light receiving element is provided with a reset means for setting the potential of the region to a predetermined potential.