JPH03257544A - Microprocessor - Google Patents

Abstract

PURPOSE:To improve the software developing efficiency by providing a means which compares the contents of a means which stores a prescribed instruction word to be interrupted with an instruction word which is fetched from outside and produces a prescribed interruption when the coincidence is obtained in the preceding comparison. CONSTITUTION:An instruction is set to a trap instruction register 4 to generate a prescribed interruption. At the same time, a prescribed instruction is read into a prefetch queue 3 by an external bus control unit 2. When the instruction is read out of the queue 3 in an execution unit 1, an instruction is also transferred to an interruption generating circuit 5. The circuit 5 compares the received instruction with a bit train that is previously set into the register 4. When the coincidence is secured in this comparison, an interruption signal is produced and sent to the unit 1. Then an interruption request is executed to the unit 1. Thus the software developing efficiency is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microprocessor, and particularly to a microprocessor having a dayback function required for software development.

[Conventional technology]

Conventionally, this type of microprocessor has had a function that generates a predetermined interrupt by accessing a specific address, as a diversion function in the development of software zero air. This is common.

[Problem to be solved by the invention]

The above-mentioned conventional microprocessor naturally has the function of generating a predetermined interrupt by accessing a known address when performing debugging during the development of software 0 air. Therefore, in recent years, when software development engineers do not directly manage addresses and require interrupts to be made by specific instructions, such as with relocatable assemblers or compilers, It is necessary to investigate the inside of the software in detail in advance, which has the disadvantage of reducing the efficiency of software development.

[Means to solve the problem]

The microprocessor of the present invention compares the contents of the means for storing a predetermined instruction word to be an interrupt target, the contents of the means for storing the instruction word, and the instruction word fetched from the outside, and if the two match, and means for generating a predetermined interrupt.

〔Example〕

Next, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram of a first embodiment of the invention. As shown in FIG. 1, this embodiment includes an execution unit 1, an external bus control unit 2 that controls bus cycles to the outside, a briffetch queue 3, and a trap instruction register that stores interrupt generation instructions. 4 and an interrupt generation circuit 5.

In FIG. 1, a trap instruction register 4 is set in advance with an instruction for generating a predetermined trap. Further, the external bus control unit 2 reads a predetermined instruction into the one-reswitch queue 3.

When the execution unit 1 reads the instruction from the switch queue 3, the instruction is also transferred to the interrupt generation circuit 5 at the same time. The interrupt generation circuit 5 includes a multi-bit/soto comparator and compares the above-mentioned transferred instruction with a bit string preset in the trap/γ-p instruction register 4. If both of them match, an interrupt signal is generated and sent to the execution unit Y, and an interrupt request to the execution unit Y is executed.

Therefore, if the instruction transferred via the execution unit (2) does not match the instruction content preset in the trap instruction register 4, no interrupt request is made to the execution unit (1).

Next, a second embodiment of the present invention will be described. FIG. 2 is a block diagram of the second embodiment. As shown in FIG. This embodiment includes an execution unit 6, an external bus control unit 7, a brieffetch queue 8, a trap instruction register 9, an interrupt generation circuit 10, and an interrupt type register U.

In this embodiment, for each trap instruction register 9, a corresponding interrupt type register 11 is provided. In the trap instruction register 9,
An instruction for generating an interrupt is set in advance, and an interrupt vector is set in the interrupt type register 11 in advance.

When a predetermined instruction is read into the blink queue 8 by the external bus control unit 7, the interrupt generation circuit 10, which is composed of a multi-bit comparator, compares the contents of the blink queue 8 and the contents of the trap instruction register 9. are compared, and if they match, an interrupt request to the execution unit 6 is generated. Of course, if there is no match, no interrupt request is issued, and at this point, the value set in the interrupt type register 11 is read depending on the interrupt vector type.

Note that in this embodiment, it is possible to change the interrupt processing for each instruction that generates a trap.

〔Effect of the invention〕

As described above in detail, the present invention enables the generation of a required interrupt by executing a specific instruction code during software development, so that the computer support work required for the software development is This has the effect of increasing efficiency.

[Brief explanation of drawings]

1 and 2 are block diagrams of first and second embodiments of the present invention, respectively. In the figure, 1.6--execution unit, 2,7
99. ...External bus control unit, 3,8-...
・Briefetch queue, 4.9...Trap instruction register, 5.10-...Interrupt generation circuit,
11... Interrupt type register.

Claims (1)

[Claims] A means for storing a predetermined instruction word to be interrupted; and a means for comparing the contents of the storing means with an instruction word fetched from the outside, and if the two match, a predetermined instruction word is stored. A microprocessor comprising means for generating an interrupt.