JPH03260735A - Confirming syste for working of parity detecting circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Application in CJI Industry The present invention relates to an operation confirmation method for a system in which a plurality of bus interface circuits are connected to a bus.

In a system in which a plurality of bus interface circuits are connected, the processing operation becomes complicated, and a parity detection circuit for each interface circuit is important in order to be able to adequately handle such complicated processing. Therefore, it is necessary to check whether the parity detection circuit operates normally.

[Conventional technology]

FIG. 4 shows a general system block diagram. In the figure, bus interface circuits io, 1+.

12 are commonly connected to the bus 2, and various signals are exchanged via the bus 2. A bus handler (bus monitoring device) 3 monitors the state of the bus 2. In such a system, when checking the operation of the parity detection circuit, for example, the bus interface circuit 1° specifies the bus interface circuit 11 using the address line and outputs an inverted signal (parity error signal) to the parity line. The status signal from the parity detection circuit of the bus interface circuit 11 was detected and its operation rs verified. In this case, an identifier (ID) for the bus interface circuit 11 is output from the bus interface circuit 1o to the address line, and each bus interface circuit checks this identifier (ID) to check whether it is designated. do.

FIG. 5 shows a schematic configuration diagram of each bus interface circuit 10-12. During normal operation (not in test mode),
The test mode signal is set to rOJ. Thereby, the parity output signal of the bus interface circuit 10 is obtained on the parity line with the same polarity via the exclusive OR circuit gate 4, and is sent to other bus interface circuits.

On the other hand, in the test mode, the test mode signal is set to "1". As a result, the polarity of the pariday signal of the bus interface circuit 1o is inverted by the exclusive OR gate 4, and an inverted signal (parity error signal) is obtained on the parity line as described above.

In this case, as described above, the identification f of the designated bus interface circuit 11 is output to the address line.

[Problem to be solved by the invention]

By the way, since the system shown in FIG. 4 has separate address lines and data lines, the structure of the bus 2 becomes a doll. Therefore, the address line is also used as the data line, and as shown in FIG. 6, the bus star h (B
By sending the command/address (C/A) to the specified bus interface circuit only at the timing of S), and then sending the data (D/D), the tA structure of the bus can be made as small as possible. The command/address has the format shown in Fig. 7 and is composed of 5ID (sending side identifier) and DID (receiving side identifier).BE is the bus end and indicates the end of data.

During normal operation, the bus interface circuit
The configuration shown in the figure (however, the address line is omitted and is also used as the data line) does not provide any support. That is, the test mode signal is
If set to OJ, a signal with the same polarity as the parity signal will be output as is ("positive" shown in Figure 6) to the valid wire, and the specified bus interface circuit 11 will be connected to the source bus interface circuit 1°. and send the status of rOKJ.

However, the bus interface circuit has the configuration shown in FIG.
However, if the address line is omitted and is also used as a data line, the following problem will occur. That is, the test mode signal is set to 1.
1, the polarity of the parity signal is inverted by the exclusive OR game h4 as described above, so the parity line receives an inverted signal (parity error signal) as shown in Figure 8.
In this case, the data line is used as both the address line and the command/address is output to the data line only at the bus start (BS) timing, so an inverted signal is output at this timing. If this happens, even if the bus interface circuit 11 is specified by a command/address, the bus interface circuit 11 will not be able to identify the address.

For this reason, the path handler 3 only returns the status of rERRJ to the bus interface circuit 1° that is the source, and there is a problem in that it is not possible to check the operation of the parity detection circuit of each bus interface circuit.

The present invention provides an operation of a parity detection circuit that can reliably confirm the operation of the parity detection circuit of a specified bus interface circuit with a small bus configuration! The purpose is to provide a method of recognition.

(Means for solving the two problems) FIG. 1 shows a diagram of the principle of the present invention. In the figure, 21 is a gate means, which receives a parity signal 202 of the bus interface circuit.
Normal rotation/inversion is controlled by a test mode signal 203. That is, the operating state changes depending on the polarity of the test mode signal @203, and the inverted signal is not output to the parity line only when the bus start signal 204 is valid, and the bus start signal 204 is no longer valid. After that, an inverted signal is output to the parity line.

(effect) During normal operation, the test mode signal 203 is set to [0].

As a result, the output of the parity conversion @202 is changed to the gate means 2.
1 and output to the parity line with the same polarity.

On the other hand, in the test mode, the test mode signal 203 is set to "1".
”. As a result, first, the bus start signal 204
When the parity signal 202 is valid, the output of the parity signal 202 is output from the gate means 2.
1, it is output without being inverted, and then the bus start signal 2
04 is no longer valid, the parity signal 202 is inverted by the gate means 21 and output. Therefore, at the timing of the bus start signal 204, data 1f120 +
The identifier of the receiving side bus interface circuit outputted to can be reliably identified by each bus interface circuit, and the operation of the parity detection circuit of the designated bus interface circuit can be correctly confirmed. Moreover, in this case, since the data line is used to send the identifier (command/address) together with the data (that is, the data line and the address line are both used), the bus can be made compact.

〔Example〕

FIG. 2 shows a block diagram of essential parts of an embodiment of the present invention.

In the figure, 10 is a bus interface circuit, which receives data signals 301. Parity signal 302. Test mode signal 303
．． Bus start signal 304° bus end signal 305. A status signal 306. Death 1~Mode signal 303
An AND gate 11 is connected to the bus start signal 304, and the AND gate 11 is connected to the parity signal 302 and the bus start signal 304.
An exclusive OR gate 4 is connected to the output signal 1 to form a parity line. The present invention is applied to an address line and a data line (shown as a data line in FIG. 2).

12 is a driver circuit, 13 is a receiver circuit, and data,
Used for sending and receiving commands/addresses. 14
is a parity generation circuit that generates parity bits based on the output timing of the receiver circuit 13. 15 is a parity generation circuit, based on the timing of transmission data,
Generates parity bit for parity check.

16 is a parity detection circuit (parity check circuit);
It is supplied with the respective outputs of the parity generation circuits 14 and 15, performs parity detection, and outputs the result, ie, NG or OK, to the status line. A bus start buffer 17 outputs a bus star 1- signal (83) at the command/address (C/A) timing of the data signal 30+ shown in FIG. 2, as shown in FIG. 1
8 is a bus end buffer, and as shown in FIG. 3, the bus end signal (8[
) is output.

Next, the operation of the main part of the present invention will be explained.

First, during normal operation, the test mode signal 303 is set to rOJ. As a result, the output of the AND gate 11 is set to "0" regardless of the bus star 1 signal (BS), and therefore the parity signal 302 is output to the parity line with the same polarity via the exclusive OR gate 4. , sent to other bus interface circuits. At this time, the command/address (C/A) is outputted as the data signal 301 at the timing of the bus start signal (BS), and the identifier of the designated bus interface circuit is outputted to the data line. The designated bus interface circuit looks at this identifier and exchanges signals with the transmission side bus interface circuit.

Next, in the test mode, the test mode signal 303 is set to “1”.
”. AND gate 11 outputs bus start signal 30
4 changes its output to “0” by bus start signal “1”
As a result, the parity signal 302 is output to the parity line as "positive" through the exclusive OR gate 4 with the same polarity as shown in FIG. Subsequently, the AND gate 11 determines that the bus start signal 304 is "0".
”, the output is set to “1”, and as a result, the polarity of the parity signal 302 is inverted by the exclusive OR gate 4, and an inverted signal (parity error signal) as shown in FIG. 3 is output to the parity line. Ru.

In this way, in the test mode, the bus start signal (BS
)'s "1" output forces one input signal of exclusive or game h4 only at this timing.
0", the parity signal 302 output at this timing is obtained on the parity line with the same polarity ("positive" shown in FIG. 3). Therefore, as shown in FIG. The output command/address (C/A) will be correctly identified by the designated bus interface circuit 11. As a result, as shown in FIG. Returns the rOKJ status to
Specified path interface]--The operation of the parity detection circuit of the path circuit 11 is correctly confirmed. That is, since a parity error occurs due to the subsequent data (D/D), the parity detection circuit of the bus interface circuit 11 returns a status of rERRJ.

In the above description, an example has been given in which the 1-circuits 4 and 11 are provided outside the bus interface circuit 10, but the effects of the present invention do not change even if they are provided inside the bus interface circuit 10.

〔Effect of the invention〕

As explained above, according to the present invention, a gate circuit that does not invert parity is installed only when the bus start signal is valid in the test mode, so that data and identifiers (commands/addresses) cannot be sent to the data line. ,
Although the bus configuration is small enough to omit the address line and serve as both the address line and the data line, the specified receiving side bus interface circuit can reliably receive the identifier in test mode, and its parity detection circuit You can confirm that it works correctly.

[Brief explanation of drawings]

Fig. 1 is a principle diagram of the present invention, Fig. 2 is a block diagram of essential parts of an embodiment of the present invention, Fig. 3 is an operation sequence in the test mode of the present invention, and Fig. 4 is a general system configuration diagram. , Figure 5 is a schematic configuration diagram of a conventional bus interface circuit, Figure 6 is an operation sequence during normal operation in a conventional example, Figure 7 is a command format, and Figure 8 is a test using a conventional configuration. This is the operation sequence in mode. In the figure, 4 is an exclusive OR gate, 10 is a bus interface circuit, 11 is an AND gate, 20+, 30+ are data signals, 202.302 is a parity signal, 203.303 is a des1~mode signal, 204.304
21 is a gate means, and 30s is a bus end signal. Principle diagram of the present invention Figure 91 Figure 0 Block diagram of the main part of the embodiment of the present invention Schematic configuration diagram of a conventional bus interface circuit Figure 5 #1 One status ErC rotation DI times vinegar

Claims (1)

[Claims] In a system in which a plurality of bus interface circuits are connected to a bus, a parity signal (20_2) of the bus interface circuit
) is provided, the gate means (21) changing the polarity of the test mode signal (20_3) according to the polarity of the test mode signal (20_3).
), the inverted signal is not output to the parity line only when the bus start signal is valid, and the inverted signal is output to the parity line after the bus start signal is no longer valid. A method for checking the operation of a parity detection circuit.