JPS6017541A - Test control system with error checking function - Google Patents

Abstract

PURPOSE:To improve the reliability of the operation and to simplify the test control circuit with error checking function, by installing the means for inhibiting the operation of the pseudo error generating means and pseudo error cause setting display means and pseudo error generating means. CONSTITUTION:The means for inhibiting the operation of the pseudo error generating means and pseudo error cause setting display means and pseudo error generating means are installed. For example, usually at the time of the operation mode, the data read out from memory 1 is inputted through the data line 8 to the ECC (error correction code) checking circuit 2 as it is and almost spontaneous errors are checked. And, at the time of the test mode, the peudo error cause setting display circuit 6 is set to ON by the pseudo error setting signal (a) from CPU, is sent to the exclusive OR gate 7 without inhibiting the signal (b) in the inhibiting circuit 13 and the error condition is forcibly generated. Next, the error is detected by the ECC checking circuit 2 and error detecting circuit 3, the ECC error cause display circuit 4 is set to ON and informed to a CPU and the pseudo error generating function is stopped.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention selectively sets a pseudo-error cause in a test of an error check function such as parity or ECC in a memory device or a data transmission system. It is easy to determine whether the detected error corresponds to a pseudo-configured error or a naturally occurring error, and it is easy to control the setting and resolution of pseudo-error causes. The present invention relates to a test control method for an error check function that includes a means for controlling the error check function.

[Length of technology]

In a data processing system or data communication system,
Since errors may occur when storing or transmitting data, data is checked using a parity or EOO (error correcting code) method.

However, there is a possibility that a failure may occur in the data checking function itself, and in that case, proper data checking will not be possible, resulting in inability to process or erroneous processing.

For cases like this, conventional methods have been provided to test the data check function by forcibly or pseudo-generating a data error, checking the state of the data error detected as a result, and then checking the data. A method is used to detect whether the data check function is normal or not based on the results.

According to this method, the first failure of the data check function is detected depending on whether normal data is determined to be error data or error data is determined to be normal data.

By the way, in order to forcibly generate a data error, it is necessary to create the cause of the error, that is, to set a pseudo failure state. However, this cause must be eliminated immediately after causing the error. Otherwise, data errors will continue to occur and cause inconvenience until the cause of the error is eliminated. For example, memory E
In the case of OO error checking, if there is data and instructions in memory, and a pseudo-error cause is set, and an error occurs in the data, an error will also be introduced in the instructions that are subsequently read, and the system will go into a runaway state. turn into. Therefore, if the cause of the error is not immediately resolved as described above after a data error occurs, testing of the data error checking function itself will be impossible.

However, if the cause of the error is immediately eliminated after a pseudo data error has occurred, it becomes impossible to determine whether or not the detected data error was intentionally generated.

Therefore, a pseudo error cause setting circuit that is reset immediately after setting the error cause, and a pseudo error cause setting display circuit that is not reset when the cause is identified by the test software are required.

FIG. 1 shows an example of a conventional test control circuit equipped with the above-mentioned data error checking function. In the same figure, 1
is a memory, 2 is an ECO check circuit, 3 is an error detection circuit, 4 is an ECC error cause display circuit, 5 is a pseudo error cause setting circuit, 6 is a pseudo error cause setting display circuit, 7 is an exclusive OR for pseudo error generation Gate, 8 is data line, 9
1 is an interrupt signal line, 10 is a pseudo error setting signal line, 11 is an error cause display reset signal line, and 12 is a pseudo error cause display read signal line. Note that each of the circuits 4, 5 and 6 can be constructed from a flip-flop.

In normal operation mode, circuits 5 and 6 are reset (OFF).
) state and exclusive OR gate 7 for pseudo-error generation
does not function, and the data bits on data line 8 read from memory 1 are directly checked by ECC check circuit 2.

The ECC check circuit 2, error detection circuit 3, and ECC error cause display circuit 4 collectively perform an error check function. The ECC error cause display circuit 4 outputs It Off as long as the data is normal, and when the error detection circuit 3 detects a data error, it is set to ON and outputs "1#".

The “work” output of this circuit 4 indicates the occurrence of a BOO error (01)
It becomes an interrupt signal to notify U.

In the dead mode, the pseudo error cause setting circuit 5 and the pseudo error cause setting display circuit 6 are set to ON via the signal line 10 by the OPU. As a result, exclusive OR
1# is input to gate 7, causing gate 7 to generate a pseudo error, inverting the value of a specific data bit in data line 8, and generating a forced I data error. Therefore, the EOC check circuit and error detection circuit 3 detects a data error, sets the ECC error cause display circuit 4 to ON, and displays the occurrence of an EOO error.

When "1" is output from the circuit 4, the pseudo error cause setting circuit 5 is immediately reset, "0" is input to the gate 7, and the error generation function is stopped.
Thereafter, no pseudo errors will be introduced into data or instructions read from the memory 1.

The OPU that has received the EOO error occurrence interrupt reads the state of the pseudo error cause setting display circuit 6 via the signal processing 2 in order to investigate the cause of the interrupt, and determines whether the EOO error is a pseudo error or whether it has occurred naturally. Performs processing to identify whether it is a specific error. After the identification process is completed, the CPU resets the circuit 6 via the signal line 11.

(Faults of Fuju's test control circuit When setting the cause of i, o, pseudo-d, error, two circuits 5 and 6 must be set to ON at the same time, the circuit becomes complicated, and the setting It has the ability to control errors.

[Object and structure of the invention]

An object of the present invention is to simplify a test control circuit for an error check function and to improve operational reliability.

Therefore, the configuration of the present invention is such that, in a data processing system equipped with an error check means and an error display means that generates an interrupt signal when an error is detected, the means for generating a pseudo error and the means for generating a pseudo error are activated. At the same time, when the pseudo error cause setting display means displays the pseudo error cause setting state, the means for suppressing the operation of the nuclear pseudo error generation means, and the error checking means detects an error and the error display means is set to ON. The present invention is characterized by comprising means for activating the inhibiting means in response to an interrupt signal output to the device, and means for simultaneously resetting the error display means and the pseudo error cause setting display means.

[Embodiments of the invention-]

1-1 Details of the present invention will be explained below based on Examples.

FIG. 2 is a configuration diagram of an error check function test control circuit according to an embodiment of the present invention. In the figure, 1 is memory, 2 is FCC
3 is an error detection circuit, 4 is an EOO error cause display circuit, 6 is a pseudo error cause setting display circuit, 7 is a pseudo exclusive OR gate for chi generation, 8 is a data line,
9 is an interrupt signal line, 10 is a pseudo error setting signal line, 11
Reference numeral 12 indicates an error cause display reset signal line, 12 indicates a pseudo error cause display read signal line, and 13 indicates a suppression circuit.

Further, FIG. 3 shows the timing of signals of each part of the circuit indicated by ``■'' and ``■'' in FIG. 2.

Next, the operational functions of the embodiment circuit of FIG. 2 will be explained with reference to FIG.

Normal operation mode (in one word, the pseudo-error cause setting display circuit 6 is reset) (OFF) state, and the signal (
Since ◇ is at the @Os level, the exclusive OR gate 7 for pseudo error generation does not function, and the data on the data line 8 read from the memory 1 is automatically A check is made for possible errors.

In the test mode, a pseudo error setting signal @ is applied from the CPU to the pseudo error cause setting display circuit 6 via the signal line 10, and the circuit 6 is set to ON. Therefore, the signal becomes °°1'', and on the other hand, since the interrupt signal ■, which is the output of the EOO error cause display circuit 4, which is reset in the initial state, is II O)l, the suppression circuit 13 The signal ■ is sent to the exclusive OR gate 7 without being inhibited. As a result, the gate 7 is functionalized and the data line 8 is sent to the exclusive OR gate 7.
Inverts the value of the second bit to force an error condition.

Therefore, the EOC check circuit 2 and the error detection circuit 3 detect the error, and the EOO error cause display circuit 4 is set to ON by the detection signal (2). As a result, the interrupt signal (2) becomes "1" and is notified to the CPU, while also being applied to the inhibit circuit 13. Therefore, the suppression circuit 13 inhibits the output signal ■ of the pseudo error -# cause setting display circuit 6, and M'+! Return i■ to 10'' -C, and stop the pseudo error generation function by gate 7.

At this time, the OPU that has received the interrupt signal (■) reads the state of the pseudo error cause setting display circuit 6 via the signal line 12, and confirms that the cause of the error is pseudo, that is, "1" of the signal (■). ”, then signal line 11
The error cause display reset signal is sent to circuits 4 and 6 through
and reset them to OFF. As a result,
The test mode is canceled and the signal ■ becomes 0#, so even if an error is detected by the post-ECO check circuit 2 or the like, the CPU identifies this as a spontaneous error.

However, the present invention can be applied to test control of any error checking function.

〔Effect of the invention〕

As described above, according to the present invention, since the circuit set during the test moto is only the pseudo-error prisoner setting table circuit, it is possible to reduce the possibility of a bj setting error occurring compared to the conventional method. In addition to improving reliability, it is possible to simplify the circuit and reduce the number of circuits required.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional error check function test control circuit, FIG. 2 is a block diagram of an error check function test control circuit according to an embodiment of the present invention, and FIG. 3 is a timing diagram of the same embodiment. In the figure, 1 is a memory, 2 is an ECC check circuit, 3 is an error detection circuit, 4 is an EOlj error-cause display, 6 is a pseudo-error cause setting display circuit, 7 is an exclusive O-gate for pseudo-error generation, 13 represents a suppression circuit. Patent Applicant Fujitsu Limited Representative Patent Attorney Fumihiro Hase (and 1 other person) Leaf 1 Figure t 3 Figure continued Amendment (at the time of request for examination) 1. Indication of the case: 1982 Patent Application No. 56114 2,
Title of the invention KEST control method 3 with error check function
Relationship with the case of the person making the amendment Patent Applicant Address: 1015 Kami Elementary School, Nakahara-ku, Yozaki City, Kanagawa Prefecture Name (522) Fujitsu Limited Representative Takuma Yamaki 4, Agent 5, Inventions increased by amendment Number: None 6, Subject of amendment: "Claims" column 7 of the specification, Contents of amendment As shown in the attached sheet, Contents of amendment 1: Patent claims stated in lines 5 to 18 of page 1 of the specification. Correct the entire range as shown in F. ``In a data processing system J comprising an error checking means and an error display means for generating an interrupt signal when an error is detected by the error checking means,'' - generates pseudo error data in which an error can be detected by the error checking means. means, pseudo error cause setting display means for activating the generating means and displaying the pseudo error cause setting state, and means for suppressing the operation of the generating means, and when the error checking means detects an error, A test control method for an error check function, characterized in that the inhibiting means is activated by an interrupt signal output from the error displaying means. 2. In the specification m, page 7, line 10 to page 8, line 1, ``Error check...Features'' are corrected as follows. ``In a data processing system that includes an error check means and an error display means that generates an interrupt signal when an error is detected by the error check means, pseudo error data that can be detected as an error by the error check means is The error checking means detects an error, and includes a means for generating a pseudo error cause, a pseudo error cause setting display means for activating the generating means and displaying a pseudo error cause setting state, and a means for suppressing the operation of the generating means. By doing so, the inhibiting means is activated by an interrupt signal output from the error displaying means. Above one crown f''-3 Kazuichi-Sho tau: (Directive) August 160, 1980 Patent application No. 56714-'r32, title of invention Error check, dest control method 2 of function 2, supplement Relationship with the case involving the person using the 1st floor Patent'(Applicant's address: Nakahara Ward, Yozaki City, Kanagawa Prefecture, Small IJJ II'),
(115th address (,522) Tomisu J Co., Ltd. Representative Ichi Yamaki Takashi 46 Agent address Nishi 1, Arakawa-ku, Tokyo] Kuroko 4-J 17th silkworm 1 yen; Shipping date 7゛°, 1982 Month 31st 6, Number of inventions increased by amendment 0 7, Subject of amendment [-Submitted on April 13, 1980]
+-WE Toyama-j-
14/13/F7 Director General Wakasugi Kazufuge 11 1. Showing 11 results 1981 5'1 Application No. 5 (I 714 No. 2, Name of investigation 1 Laichienoku function test control method 3 , Relationship to the case of the person making the amendment Patent applicant address: L Elementary School, Nakahara-ku, Yozaki-shi, Kanagawa Prefecture [11-1015] Name (522) Fujitsu Co., Ltd. Representative: Takashi Yamao 4, Agent address: Tokyo 4-17-1-5 Nishi I Kobori, Miyako Arakawa-ku, Number of inventions increased by amendment: None 6, Subject of amendment: “Claims” in the specification. “Detailed description of the invention” column 7: Contents of the amendment As shown in the attached sheet

Claims (1)

[Claims] In a data processing system comprising an error check means and an error display means for generating an interrupt signal when an error is detected by the error check means, means for generating pseudo error data in which an error can be detected by the error check means; Providing pseudo error cause setting display means for activating the generating means and displaying a pseudo error cause setting state, and means for suppressing the operation of the generating means,
When the error checking means detects an error, the inhibiting means is activated by an interrupt signal output from the error displaying means, and the error displaying means and the pseudo error cause setting displaying means are reset. Test control method for error checking function.