JPH03262020A - Power failure detecting circuit - Google Patents

Abstract

PURPOSE:To shorten the time from the occurrence of the power failure to the detection of the power failure and to save a large amount of data from a CPU on the side of a nonvolatile memory in case of a power failure by providing a pulse converting circuit which converts the waveform of an AC power source into a pulse signal and a period detecting circuit which detects its pulse intervals. CONSTITUTION:When the AC power source is disconnected, the pulse width of the pulse converting circuit 4 connected to this AC power source varies and the pulse period detecting circuit 6 detects the extension of its pulse period and sends an interruption request signal to a CPU 7. The CPU 7 which receives the interruption request signal receives this signal as an interruption which can not be masked and saves its internal data in the nonvolatile memory 8. Consequently, the power failure is detected in its early stage and it can take a long time to save the data of the CPU 7.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a circuit that operates using an AC power source and detects a power outage in a device equipped with a CPU, and relates to an improvement in the data saving operation of the CPU after a power outage. It is.

<Prior Art> Fig. 3 is a partial configuration diagram showing an example of a conventional power outage detection circuit. A capacitor 2 smoothes the output, and 3 is a DC/DC converter that creates a stable voltage, for example 5, necessary for logic circuit operation from the DC voltage obtained across the rectifying and smoothing capacitor C1. Capacitor C2 is connected.

The stable output voltage of this DC/DC converter 3 is CP
It is supplied to U etc. Here, assuming that the voltage across the capacitor C2 (potential at point A) is 5V, if a power outage is detected by detecting a drop in the potential at point A, the potential at point A until the CPU stops is 4V. It will look like the figure.

FIG. 4 is a time chart showing potential changes at point A in FIG. 3 when the AC power supply is out of power.

When the AC power supply 1 has a power outage at point D in FIG. operation stops. DC/D
When capacitor C2 starts discharging at point E, where C converter 3 stops, the potential at point A decreases. Here, a comparator or the like is connected in advance to both ends of the capacitor C2, so that a power outage is detected when the potential at point A becomes lower than V, (point F). Also, suppose that the CPU connected to this circuit is configured to stop when the potential at point A becomes smaller than V2 (point G), t in Figure 6,
t2 is the time from point E to point F and from point F to point G, and while the operation of the DC/DC converter 3 is stopped,
The time t1 until a power outage is detected is a time that must be shortened, and the time t2 from when a power outage is detected until the operation of the CPU is stopped is a time that must be extended.

Figure 5 shows point B in Figure 3 when the AC power supply is out of power.
That is, it is a time chart showing potential changes at the output end of the rectifier circuit 2. Here, in a stable state, the potential at point B is assumed to be V. In this case, when a power outage occurs at point H in Figure 5, the capacitor C1 discharges at the same time as the power outage occurs at point H. begins, so the potential at point B decreases. Here, a power outage is detected by a comparator connected to the capacitor C1 when the potential at point B becomes smaller than v3 (one point). Also, the potential at point B is V4
(point J), the DC/DC converter 3 stops operating. The point in the diagram is C.
The point at which the PU stops is not determined by the potential at point B, so the potential is not displayed.
1 is the time to reach point H or 4 from point 1 to point 1, and CP after power outage.
In terms of saving data in U, the time t3 from the occurrence of a power outage until the power outage is detected must be shortened, and the time t4 from the time a power outage is detected until the CPU stops operating must be extended. It's an unprecedented time.

<Problems to be Solved by the Invention> In the conventional example as shown in FIG. 3, the voltages V1, V2, v3, and V4 in FIGS. 4 and 5 cannot usually be changed. When detecting a power outage based on the potential at point A, the speed of potential drop must be reduced in order to lengthen the time t2 until the CPU stops.In this case, if the capacitance of capacitor C2 is increased, Although t2 becomes longer, there is a problem in that it becomes longer than tl, which does not need to be increased. Furthermore, when detecting a power outage based on the potential at point B as shown in Figure 5, in order to lengthen the time tl until the CPU stops, the capacitance of capacitor C1 must be increased.In this case, t4 must be increased. However, there is a problem that the length increases to t3, which is not necessary.

The present invention was made to solve such problems, and an object of the present invention is to provide a power failure detection circuit that can detect the occurrence of a power failure as soon as possible and can prolong the data saving time of the CPU.

Means for Solving the Problems> The present invention provides a power outage detection circuit that detects a power outage in a device equipped with a CPU that operates using a DC voltage obtained by rectifying and smoothing an AC power supply, in which input and output are isolated. , monitors the pulse conversion circuit that converts the waveform of the alternating current source into a pulse signal, and the pulses generated by this pulse conversion circuit, and sends an interrupt request signal when a pulse interval longer than the normal pulse period is detected. A generated pulse period detection circuit; a CPU that receives an interrupt request signal from the pulse period detection circuit as a non-maskable interrupt and performs an internal data saving operation; and a non-volatile memory for saving data from the CPU. , detecting a drop in the DC voltage supplied to the CPU, and
A power outage detection circuit is characterized in that it includes a reset signal generation circuit that generates a reset signal to a PU and stops the operation of the CPU.

In the present invention, when the AC power supply fails,
The pulse width of the pulse conversion circuit connected to this AC power source changes, and the pulse period detection circuit detects the extension of the pulse period and sends an interrupt request signal to the CPU. The CPU that receives this interrupt request signal receives this signal as a non-maskable interrupt and saves internal data to E2PROM (non-volatile memory).

Here, the reset signal generation circuit detects a drop in the DC voltage supplied to the CPU, generates a reset signal to the CPU, and the CPU stops operating.

<Example> The present invention will be described in detail below using the drawings.

FIG. 1 is a circuit configuration diagram of an embodiment of a power outage detection circuit according to the present invention. In FIG. 0, the same components as in FIG. 3 are designated by the same numbers and their explanations are omitted. In FIG. In the pulse conversion circuit 4, R1, R2, and R3 are resistors, Tr is a transistor, FD is a photodiode,
FTr is a phototransistor, one end of R4 is connected to the collector side of the phototransistor FTr, and the other end is connected to DC/
This is a pull-up resistor to which the output voltage Vcc of the DC converter is applied. 5 is a steresis comparator connected to the pulse conversion circuit 4, and 6 is a pulse period detection circuit connected to the pulse conversion circuit 4 via the steresis comparator 5, which detects the period of the input pulse and determines the regular pulse period. When a longer pulse interval is detected, it is determined that a power outage has occurred, and an interrupt request signal NHI is sent to the CPU 7. 7 is a request signal M from the pulse period detection port NI6
The CPU accepts HI as a non-maskable signal and saves the data. 8 is a non-volatile memory E2PROM into which the data to be saved is written. This E2PROM 8 is electrically rewritable and takes several ms to rewrite. mathematician ms
It requires 9 is DC/DC converter 3
detects a drop in the output Vcc of the
This is a reset signal generation circuit that sends the following to the CPU.

Next, the present invention will be explained in detail using FIGS. 1 and 2. FIG. 2 is a time chart showing the operation of the power failure detection circuit according to the present invention. First, consider the state before the power outage occurs before t5 in FIG. 2(a).

FIG. 2(a) shows the output voltage of the AC power supply 1, which is, for example, a sine wave with a commercial frequency of 50 Hz.

While a stable sine wave is being output from the AC power source 1 in this way (before t5), the DC/DC converter 3
A stable voltage source Vcc is supplied to the circuit as shown in Figure (e). Further, at this time, the pulse conversion circuit 4 outputs a pulse signal with a period of about 20 m5. At this time, when a current flows in the direction of arrow A in the figure, the transistor Tr is turned on, so the current flows through the photodiode FD, the phototransistor FTr is turned on, and the pulse conversion circuit 4 outputs a low level. On the other hand, when a current flows in the direction of arrow B, the transistor Tr is turned off, so no current flows through the photodiode FD, and the phototransistor FTr is turned off and outputs a high level. This pulse signal is used to make the pulse width constant using the steresis comparator 5.
A waveform as shown in FIG. 2(b) is output. The pulse cycle detection port 86 detects the pulse cycle. Here, when a power outage occurs in the AC power supply, the transistor Tr is turned off, the output of the pulse conversion circuit 4 remains at a high level (Vcc is still at a high level), and the pulse period detection circuit 6 is turned off. If the period of the output pulse of the bisteresis comparator 5 exceeds a predetermined period, it is regarded as a power outage and an interrupt request signal NHI is sent to the CPU 7. The reset signal generation circuit 9 receives the output voltage V of the DC/DC converter 1.
It monitors the drop in cc, and when a drop in voltage is detected, the CP
A reset signal RESET is generated to stop the operation of U7.

Now, consider the case where a power outage occurs at time t5 in FIG. 2(a). When a power failure occurs at t5, the phototransistor FTr of the pulse conversion circuit 4 is turned off, and the input signal of the pulse period detection circuit 6 continues to maintain a high level as shown in FIG. 2(b). Here, the pulse cycle detection circuit 6 is configured to generate an interrupt request signal MHI when the pulse cycle exceeds 20m5+α. Therefore, the second (
As shown in c), the N)41 output signal of the pulse period detection circuit 6 is at a high level as long as the pulse period does not exceed 20m5+α, and when it exceeds 20m5+α at time t6, it is regarded as a power outage, and the interrupt request signal is enabled. becomes low level,
Requests an interrupt to the CPU. The CPU 7 receives this interrupt signal as a non-maskable interrupt and transfers the data to E2.
Proceed to save to PROM.

On the other hand, since the smoothing capacitor C1 in FIG. 1 starts discharging at the same time as the power outage occurs at time t5, the input voltage of the DC/DC converter 3 starts to decrease from t5 in FIG. 2(d).

Thereafter, at time t in FIG. 2(d), the voltage across the capacitor C reaches V4, and the 1 DC/DC converter 3 stops operating. DC/DC
At the same time as the operation of the converter 3 stops at t7, the capacitor C2 starts discharging, and the output voltage Vcc starts to decrease as shown in FIG. 2(e). The reset signal RESET of the reset signal generating circuit 9 outputs a high level while the output voltage of the DC/DC converter is higher than, for example, Vo in FIG. RESET falls and stops the CPU 7.

Therefore, the time T from when the pulse period detection circuit 6 detects the power failure at t6 until the CPU 7 stops is a sufficiently long time that the CPU 7 can use for data saving. In other words,
The time T available for data saving is the capacitor C in Figure 1.
1. The length can be increased by increasing the capacitance of C2.

<Effects of the Invention> As described above in detail, the present invention realizes a circuit that can save a large amount of data before the CPU is stopped after a power outage. In other words, the time from the occurrence of a power outage until the power outage is detected is a short time required for the pulse period detection circuit to overcount by a predetermined time longer than the normal pulse period. Accordingly, by increasing the capacitance of the capacitor connected to the input/output terminal of the DC/DC converter, it is possible to lengthen the time from when a power failure is detected until the CPU is reset. Therefore, when a power outage occurs, a large amount of data can be saved from the CPU to the nonvolatile memory.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram of an embodiment of a power outage detection circuit according to the present invention, FIG. 2 is a time chart showing the operation of the circuit in FIG. 1, and FIG. 3 is a partial configuration diagram of a conventional power outage detection circuit. Figure 4 is a time chart showing the potential change at point A in Figure 3 when the AC power supply is out of power, and Figure 5 is a time chart showing the potential change at point B in Figure 3 when the AC power supply is out of power. FIG. 1... AC power supply 2... Rectifier circuit 3...
DC/DC converter 4...Pulse conversion circuit 5...Hysteresis comparator 6...Pulse period detection circuit 7...CPU 8...E2PROM9
...Reset signal generation circuit C, C2...Capacitor R1, R2, R3, R4...Resistor '1'r...Transistor FD...Photodiode FTr...Phototransistor Fig. 5

Claims (1)

[Scope of Claims] A power outage detection circuit for detecting a power outage in a device equipped with a CPU that operates using a DC voltage obtained by rectifying and smoothing an AC power source, wherein the input and output are insulated and the waveform of the AC power source is a pulse conversion circuit that converts into a pulse signal; a pulse period detection circuit that monitors the pulses generated by the pulse conversion circuit and generates an interrupt request signal when a pulse interval longer than a normal pulse period is detected; A CPU that receives an interrupt request signal from the pulse period detection circuit as a non-maskable interrupt and performs an internal data saving operation, a non-volatile memory for saving data from the CPU, and a direct current supplied to the CPU. Detects voltage drop and
A power outage detection circuit comprising: a reset signal generation circuit that generates a reset signal to a PU and stops the operation of the CPU.