JPH03272191A - Printed wiring board - Google Patents

Printed wiring board

Info

Publication number
JPH03272191A
JPH03272191A JP7246090A JP7246090A JPH03272191A JP H03272191 A JPH03272191 A JP H03272191A JP 7246090 A JP7246090 A JP 7246090A JP 7246090 A JP7246090 A JP 7246090A JP H03272191 A JPH03272191 A JP H03272191A
Authority
JP
Japan
Prior art keywords
board
wiring board
printed wiring
insulating
electrically connected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7246090A
Other languages
Japanese (ja)
Inventor
Hirobumi Nakamura
博文 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP7246090A priority Critical patent/JPH03272191A/en
Publication of JPH03272191A publication Critical patent/JPH03272191A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0286Programmable, customizable or modifiable circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038Through-connections; Vertical interconnect access [VIA] connections

Landscapes

  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

PURPOSE:To obtain a printed wiring board of high density by a method wherein fine wires formed of electrical conductive material are arranged at a regular interval as buried in a board so as to connect circuit patterns when the circuit pattern is formed on both the front and the rear of an insulating board to form a printed wiring board, and the patterns formed on the front and the rear of the board are electrically connected. CONSTITUTION:Copper fine wires 1, 5-50mum in diameter, are arranged at a regular interval as buried in an insulating board 2 in a vertical direction, and an insulating resin 5 is formed on both the front and the rear of the insulating board excluding parts which are to be electrically connected. Then, optional circuit patterns 7 are formed on the parts which are required to be electrically connected and located on both the front and the rear of the board and the upside of the insulating resin 5, and a solder resist 6 is provided to both the front and the rear of the board excluding connecting soldered points. By this setup, through-holes used for electrically connecting the front and the rear of a printed wiring board can be dispensed with, the wiring board can be easily cleaned after it is mounted with components, and the board can be improved in density.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は印刷配線板に関し、特に絶縁基板の表裏両面の
回路パターンの電気導通を絶縁基板に埋込まれた電気導
通材料により行う印刷配線板に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a printed wiring board, and particularly to a printed wiring board in which electrical continuity between circuit patterns on both the front and back surfaces of an insulating substrate is achieved by an electrically conductive material embedded in the insulating substrate. Regarding.

〔従来の技術〕[Conventional technology]

従来、この種の印刷配線板は、第3図に示す如く、絶縁
基板4に孔を穿孔し、孔の内壁及び表面に電気導伝性金
属を析出させ、回路パターン7及びスルホール8を形成
し、印刷配線板の表裏両面の導通を行っていた。
Conventionally, this type of printed wiring board has been produced by drilling holes in an insulating substrate 4 and depositing electrically conductive metal on the inner wall and surface of the hole to form circuit patterns 7 and through holes 8, as shown in FIG. , conduction was performed on both the front and back sides of the printed wiring board.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかし、上述した従来の印刷配線板は、次のような欠点
がある。
However, the conventional printed wiring board described above has the following drawbacks.

1)印刷配線板の表裏両面の電気導通を絶縁基板に孔を
穿孔し、スルホールを形成して行っているため、高密度
な印刷配線板を設計する際に、スルホールに大きく場所
を占有されるため、高密度な印刷配線板の設計ができな
い。
1) Electrical continuity between the front and back sides of a printed wiring board is achieved by drilling holes in the insulating substrate to form through holes, so when designing a high-density printed wiring board, the through holes take up a large amount of space. Therefore, it is not possible to design high-density printed wiring boards.

2)孔を穿孔する工程において、高密度な印刷配線板は
非常に多くのスルホールを必要とするため、非常に工数
がかかる。
2) In the process of drilling holes, a high-density printed wiring board requires a large number of through holes, which requires a large number of man-hours.

3)スルホールは貫通孔となっているため部品実装時の
フラックス及びはんだの吹き上がりがある。また、部品
実装後のフラックス洗浄工程でスルホールにたまったフ
ラックスの洗浄性か悪い。
3) Since the through hole is a through hole, flux and solder may blow up when mounting components. Also, cleaning performance of flux accumulated in through holes during the flux cleaning process after component mounting is poor.

本発明の目的は、高密度な設計が可能で、少い工数て製
造ができ、部品実装時にフラックス及びはんだの吹き上
がりがなく、洗浄性の良い印刷配線板を提供することに
ある。
An object of the present invention is to provide a printed wiring board that allows for high-density design, can be manufactured with fewer man-hours, does not cause flux and solder to blow up during component mounting, and is easy to clean.

〔課題を解決するための手段〕[Means to solve the problem]

本発明は、絶縁基板の表裏両面に回路パターンが形成さ
れた印刷配線板において、前記絶縁基板の表裏両面の前
記回路パターンを結ぶように直径が5〜50μmの細線
状の電気導通材料を一定間隔に前記絶縁基板に埋込み配
置し、前記電気導通材料により、前記絶縁材料の表裏両
面の前記回路パターンの電気導通が行われる。
The present invention provides a printed wiring board in which a circuit pattern is formed on both the front and back surfaces of an insulating substrate, in which thin wire-shaped electrically conductive materials having a diameter of 5 to 50 μm are arranged at regular intervals so as to connect the circuit patterns on both the front and back surfaces of the insulating substrate. The circuit pattern is embedded in the insulating substrate, and the electrically conductive material provides electrical continuity between the circuit patterns on both the front and back surfaces of the insulating material.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
Next, embodiments of the present invention will be described with reference to the drawings.

第1図は本発明の第コの実施例の縦断面図である。FIG. 1 is a longitudinal sectional view of a fourth embodiment of the present invention.

第1の実施例は、第1図に示すように、直径か5〜50
μmの銅細線1−を垂直方向に一定間隔に配置し埋込ん
だ絶縁基板2の表裏両面に、表裏両面の導通を行う箇所
を除き絶縁樹脂5を形成し、表裏両面の導通を行う箇所
と前記絶縁樹脂5の上面に任意の回路パターン7を形成
し、はんだ接続箇所を除く表裏両面にソルダレジスト6
を形成する。
The first embodiment has a diameter of 5 to 50 mm, as shown in FIG.
An insulating resin 5 is formed on both the front and back sides of an insulating substrate 2 in which micron copper wires 1- are arranged vertically at regular intervals and embedded, except for the areas where conduction is to be made between the front and back sides. An arbitrary circuit pattern 7 is formed on the upper surface of the insulating resin 5, and a solder resist 6 is applied on both the front and back surfaces excluding the solder connection points.
form.

第2図は本発明の第2の実施例の縦断面図である。FIG. 2 is a longitudinal sectional view of a second embodiment of the invention.

第2の実施例は、第2図に示すように、直径が5〜50
μmの金相線9を垂直方向に一定間隔に配置し埋込んだ
絶縁基板3の表裏両面に、表裏両面の導通を行う箇所を
除き絶縁樹脂5を形成し、表裏両面の導通を行う箇所と
前記絶縁樹脂5の上面に任意の回路パターン7を形成し
、はんだ接続箇所を除く表裏両面にツルタレジス1〜6
を形成する。
The second embodiment has a diameter of 5 to 50 mm, as shown in FIG.
Insulating resin 5 is formed on both the front and back sides of the insulating substrate 3 in which μm gold-phase wires 9 are arranged and embedded at regular intervals in the vertical direction, except for the places where conduction is to be made on both the front and back sides. An arbitrary circuit pattern 7 is formed on the upper surface of the insulating resin 5, and Tsuruta resists 1 to 6 are formed on both the front and back surfaces excluding the solder connection points.
form.

〔発明の効果〕〔Effect of the invention〕

以上説明した様に本発明によれば、次に列挙する効果が
ある。
As explained above, the present invention has the following effects.

1)孔をあけてスルホールを形成して印刷配線板の表裏
両面の導通が行われないため、スルホールによる回路パ
ターン配線場所が狭くなることがなく、高密度な印刷配
線板が設計できる。
1) Since conduction is not performed between the front and back surfaces of the printed wiring board by forming through holes, the circuit pattern wiring area does not become narrow due to through holes, and a high-density printed wiring board can be designed.

2)表裏両面導通用にスルホールを必要としないため、
孔あけの工数を節減することができる。
2) No through holes are required for both front and back sides, so
The man-hours for drilling can be reduced.

3)スルホールという貫通孔を必要としないため、部品
実装時のフラックス及びはんだ吹き上がりがない。また
、部品実装後のフラックス洗浄工程でスルポールといっ
た孔がないための洗浄性が良い。
3) No through-holes are required, so there is no flux or solder blown up during component mounting. In addition, cleaning performance is good because there are no holes such as pores in the flux cleaning process after component mounting.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の第1の実施例の縦断面図、第2図は本
発明の第2の実施例の縦断面図、第3図は従来の印刷配
線板の一例の縦断面図である。 1・・・銅細線、2,3.4・・・絶縁基板、5・・・
絶縁樹脂、6・・ソルダレジスト、7・・・回路パター
ン、8・・・スルホール、9・・・金細線。
FIG. 1 is a longitudinal sectional view of a first embodiment of the present invention, FIG. 2 is a longitudinal sectional view of a second embodiment of the invention, and FIG. 3 is a longitudinal sectional view of an example of a conventional printed wiring board. be. 1... Copper thin wire, 2, 3.4... Insulated substrate, 5...
Insulating resin, 6...Solder resist, 7...Circuit pattern, 8...Through hole, 9...Gold wire.

Claims (1)

【特許請求の範囲】[Claims] 絶縁基板の表裏両面に回路パターンが形成された印刷配
線板において、前記絶縁基板の表裏両面の前記回路パタ
ーンを結ぶように直径が5〜50μmの細線状の電気導
通材料を一定間隔に前記絶縁基板に埋込み配置し、前記
電気導通材料により、前記絶縁材料の表裏両面の前記回
路パターンの電気導通を行ったことを特徴とする印刷配
線板。
In a printed wiring board in which circuit patterns are formed on both the front and back sides of an insulating substrate, thin wire-shaped electrically conductive material having a diameter of 5 to 50 μm is spaced at regular intervals on the insulating substrate so as to connect the circuit patterns on both the front and back sides of the insulating substrate. 1. A printed wiring board, characterized in that the circuit pattern is embedded in the insulating material and electrically conducts the circuit pattern on both the front and back surfaces of the insulating material by the electrically conductive material.
JP7246090A 1990-03-20 1990-03-20 Printed wiring board Pending JPH03272191A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7246090A JPH03272191A (en) 1990-03-20 1990-03-20 Printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7246090A JPH03272191A (en) 1990-03-20 1990-03-20 Printed wiring board

Publications (1)

Publication Number Publication Date
JPH03272191A true JPH03272191A (en) 1991-12-03

Family

ID=13489937

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7246090A Pending JPH03272191A (en) 1990-03-20 1990-03-20 Printed wiring board

Country Status (1)

Country Link
JP (1) JPH03272191A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6093476A (en) * 1997-05-02 2000-07-25 Shinko Electric Industries Co., Ltd. Wiring substrate having vias
CN111223833A (en) * 2020-01-10 2020-06-02 四川豪威尔信息科技有限公司 Integrated circuit structure and forming method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6093476A (en) * 1997-05-02 2000-07-25 Shinko Electric Industries Co., Ltd. Wiring substrate having vias
CN111223833A (en) * 2020-01-10 2020-06-02 四川豪威尔信息科技有限公司 Integrated circuit structure and forming method thereof

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