JPH0327531A - Manufacturing method of semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a bipolar transistor having a shallow base region.

[Conventional technology]

Conventionally, methods for forming the base region of a bipolar transistor include a method in which impurity atoms are injected into the collector region by ion implantation, and a method in which impurity atoms are diffused from a polycrystalline silicon film or the like by thermal diffusion.

FIGS. 2(a) and 2(b) show the latter method of forming the base region in the order of steps.

First, as shown in FIG. 2(a), an N-type collector region 22 is formed on a P-type silicon substrate 21, an N-type epitaxial layer 23 is further formed on this, and a thick silicon layer is formed on a part of the N-type collector region 22. The oxide film 24 is selectively formed to isolate the elements. Then, a P-type polycrystalline silicon film 25 and a silicon oxide film 26 are formed on this silicon oxide film 24 and selectively etched. Moreover, this polycrystalline silicon film 25
A side wall 27 of a silicon oxide film is formed on the side surface of the substrate.

Thereafter, P-type impurity atoms are diffused from the polycrystalline silicon film 25 to form a compensation base region 28.

Then, a polycrystalline silicon film 29 is formed in a region including between the side walls.

Next, as shown in FIG. 2(b), a polycrystalline silicon film 2
P-type impurity atoms, such as boron atoms, are added to 9 by ion implantation and diffused into an ebitaxial layer by thermal diffusion to form base region 3o.

Next, N-type impurity atoms, such as arsenic atoms, are added to the polycrystalline silicon film 29 by ion implantation, and then into the base region by thermal diffusion to form the vine region 31. At this time, the base region 3o becomes the compensation base region 2 due to lateral diffusion.
It is necessary to determine the diffusion conditions so as to connect to 8.

[Problems to be Solved by the Invention] The above-described conventional method for manufacturing a bipolar I transistor has the following problems.

When the Hess region is formed using the former ion implantation method,
Curve a in Figure 3 due to the channeling phenomenon of ion implantation.
A tail occurs in the P-type impurity profile, making it difficult to form a shallow junction.

Furthermore, in the latter method shown in FIG. 2, in which impurity atoms are diffused from a polycrystalline silicon film to form a haze region, impurity atoms are introduced from the polycrystalline silicon film 29 by thermal diffusion. A shallow base layer without a tail can be formed as shown in curve b. However, due to the large effective film thickness at the peripheral portion of the polycrystalline silicon film 29,
Diffusion of impurity atoms is suppressed, and the base depth at the periphery of the base region becomes even shallower. Therefore, the compensation base area 2
8 and the base region 30 becomes weaker, causing problems such as an increase in base resistance.

In this case, if the polycrystalline silicon film 29 is thinned in order to promote the diffusion of impurity atoms in the peripheral area, the ivy-like shape will result in a high concentration when arsenic atoms are diffused from the same polycrystalline silicon film. Due to the diffusion of arsenic atoms, the concentration of arsenic increases in the peripheral area, and the diffusion also progresses in the lateral direction, reducing the effective base film thickness in the peripheral area, resulting in punch-through between the collector and the straw ivy. occurs.

It is an object of the present invention to solve the above-mentioned problems and to provide a method for manufacturing a bipolar transistor having a suitable shallow base region.

[Means to solve the problem]

In the method of manufacturing a semiconductor device of the present invention, after forming a compensation base region using a first polycrystalline silicon film, the first
forming a second polycrystalline silicon film containing impurities of the opposite conductivity type in a region surrounded by sidewalls formed on the sides of the polycrystalline silicon film; and forming a semiconductor layer from this second polycrystalline silicon film. forming a base region by diffusing impurities;
A step of forming a third polycrystalline silicon film overlying the second polycrystalline silicon film, introducing an impurity of one conductivity type into the third polycrystalline silicon film, and introducing this impurity into a second polycrystalline silicon film. A step of diffusing into the heath region through the polycrystalline silicon film to form the ivy region is performed.

[Effect]

In this manufacturing method, the second polycrystalline silicon film is used to form the base region, and the second and third polycrystalline silicon films are used to form the vine region. The thickness of the polycrystalline silicon film can be made thicker than the film thickness when forming the base region, suppressing emitter diffusion and preventing punch-through.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) to 1(e) are cross-sectional views showing an embodiment of the manufacturing method of the present invention in order of T.

First, as shown in FIG. 1(a), arsenic atoms are selectively diffused into a P-type silicon substrate 1 to form an N-type collector region 2, and an N-type epitaxial layer 3 is formed on this to a thickness of 1 μm. to take shape. Furthermore, a silicon oxide film 4 for element isolation is formed on the surface of this N-type epitaxial layer 3 by selective oxidation.
form.

Next, as shown in FIG. 1(b), a first polycrystalline silicon film 5 is deposited to a thickness of 2,500 nm using the CVD method, and this is selectively oxidized to form a silicon oxide film 6. The silicon film 5 is insulated and separated. Then, boron atoms are added to a part of the first polycrystalline silicon film 5 by ion implantation to form a P-type polycrystalline silicon film 5a. Similarly, arsenic atoms or phosphorus atoms are added to other parts of the polycrystalline silicon film 5 by ion implantation or diffusion to form an N-type polycrystalline silicon film 5b. Thereafter, a silicon oxide film 7 is deposited to a thickness of 2000 mm over the entire surface by CVD.

Next, as shown in FIG. 1(c), heat treatment is performed to diffuse boron atoms from the P-type polycrystalline silicon film 5a into the epitaxial long layer 3, forming a P-type compensation base region 9.

At this time, at the same time, arsenic atoms or phosphorus atoms are diffused from the N-type polycrystalline silicon film 5b into the epitaxial extrusion layer 3,
The collector connection layer 10 is shaped.

Further, holes are selectively opened in the base type tcwA region of the silicon oxide film 7 and the P-type polycrystalline silicon film 5a by an anisotropic etching method to expose the epitaxial layer 3. And CV
After a silicon oxide film is deposited to a thickness of 3000 mm on the entire surface by the D method, this is etched by an anisotropic etching method to form a side wall 8 by leaving the silicon oxide film on the side surface of the opening. Further, a second polycrystalline silicon film 11 is deposited to a thickness of 1000 nm over the entire surface including the openings by CVD, and boron atoms are added to this polycrystalline silicon film 11 by ion implantation. Then, heat treatment at 950°C is performed to remove boron atoms from the second polycrystalline silicon film 11 in an evitaxial or long layer 3.
to form the base region 12.

Next, as shown in FIG. 1(d), a third
A polycrystalline silicon film 13 is deposited to a thickness of 2000 nm and integrated with the second polycrystalline silicon film 11. Then, arsenic atoms are added to this third polycrystalline silicon film 13 by ion implantation, and heat treatment is performed at 900°C to transfer arsenic atoms from the third polycrystalline silicon film 13 to the second polycrystalline silicon film. 11 and further through this to the base region 12
The ivy spreads inside and forms the ivy area 14. This heat treatment is controlled so that the arsenic concentration around the hole is lower than in the center of the hole. After that, the third,
The second polycrystalline silicon film 13.11 is sequentially and selectively etched.

Thereafter, as shown in FIG. 1(e), a silicon oxide film 15 as an interlayer insulating film is deposited to a thickness of 1000 nm using the CVD method, holes are selectively formed in this film, and an aluminum electrode 16 is then deposited. Selective form and collector. Use each electrode for the base and the vine.

According to this manufacturing method, when forming the heath region 12,
Since boron atoms are ion-implanted into the second polycrystalline silicon film 11 and then diffused, the diffusion occurs through the relatively thin polycrystalline silicon film, and there is no significant decrease in boron atom concentration. , the compensation base region 9 and the base region 12 are well connected, and an increase in base resistance is prevented.

On the other hand, when shaping the engineered ivy region 14, a third polycrystalline silicon film 13 is formed overlying the second polycrystalline silicon film l1, and arsenic atoms, etc. are added to the thickened polycrystalline silicon film. Since ions are implanted and diffused, the diffusion distance of arsenic atoms in the polycrystalline silicon film at the periphery becomes longer, and the arsenic concentration decreases. This suppresses the diffusion of arsenic around the base region and prevents punch-through between the collector and emitter.

〔Effect of the invention〕

As explained above, the present invention utilizes only the second polycrystalline silicon film when forming the base region.
This promotes base diffusion, provides sufficient connection between the base region and the compensating base region, and prevents an increase in base resistance.

In addition, since the second and third polycrystalline silicon films are used to form the engineered ivy region, the film thickness of the polycrystalline silicon film is increased, and the engineered It is possible to suppress the concentration of and prevent the punch-through phenomenon between the collector and emitter.

[Brief explanation of drawings]

FIGS. 1(a) to (e) are cross-sectional views showing one embodiment of the present invention in the order of manufacturing steps, and FIGS. 2(a) and (b) 910 are cross-sectional views showing some steps of a conventional manufacturing method. FIG. 3 is a profile diagram of the impurity concentration in the base region. DESCRIPTION OF SYMBOLS 1... P-type silicon substrate, 2... N-type collector region, 3... N-type epitaxial or long layer, 4... silicon oxide film, 5... l-th polycrystalline silicon film, 5a・・・
- P-type polycrystalline silicon film, 5b... N-type polycrystalline silicon film, 6... silicon oxide film, 7... silicon oxide film, 8... side wall, 9... compensation base region, 10・・・
- Collector connection layer, l1... second polycrystalline silicon film, l2... base region, 13... third polycrystalline silicon film, l4... emitter region, 15... silicon oxide film , l6... Al≧Nium electrode, 21... P-type silicon substrate, 22... N-type collector region, 23...
- N type epitaxial long layer, 24... silicon oxide film, 25... polycrystalline silicon film, 26... silicon oxide film, 27... side wall, 28... compensation base region,
29... Polycrystalline silicon film, 30... Base region,
31...Emitter region. 11 Castle

Claims (1)

[Claims] 1. Selectively forming a first polycrystalline silicon film containing impurities of an opposite conductivity type on a semiconductor layer in which a collector region of one conductivity type is formed, and introducing impurities from this polycrystalline silicon film into the semiconductor layer. a step of diffusing to form a compensation base region; a step of forming a sidewall of an insulating film on the side surface of the polycrystalline silicon film; a step of forming a silicon film, a step of diffusing impurities from the second polycrystalline silicon film into the semiconductor layer to form a base region, and a step of forming a third polycrystalline silicon film on the second polycrystalline silicon film. a step of forming films in a stacked manner, and introducing an impurity of one conductivity type into the third polycrystalline silicon film, and diffusing this impurity into the base region through the second polycrystalline silicon film to form an emitter region. 1. A method of manufacturing a semiconductor device, the method comprising: forming a semiconductor device.