JPH032786U - - Google Patents
Info
- Publication number
- JPH032786U JPH032786U JP6292989U JP6292989U JPH032786U JP H032786 U JPH032786 U JP H032786U JP 6292989 U JP6292989 U JP 6292989U JP 6292989 U JP6292989 U JP 6292989U JP H032786 U JPH032786 U JP H032786U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- circuit
- reference voltage
- outputs
- differential amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000926 separation method Methods 0.000 claims description 3
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 2
- 239000002131 composite material Substances 0.000 claims 2
- 238000001514 detection method Methods 0.000 claims 2
- 239000000203 mixture Substances 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Landscapes
- Image Processing (AREA)
- Closed-Circuit Television Systems (AREA)
- Burglar Alarm Systems (AREA)
- Emergency Alarm Devices (AREA)
- Image Analysis (AREA)
Description
第1図は本考案の一実施例に係る監視カメラ装
置の回路構成を示す図、第2図は感知領域の設定
方式を示す図、第3図はタイムチヤートである。
2……カメラ部、8……モニター部、10……
同期分離回路、12……ウインドウ設定回路、2
4……第1積分ホールド回路、26……第2積分
ホールド回路、28……差動増幅器、30……タ
イミング信号発生回路、38……ウインドウコン
パレータ、48……報知回路、50……第1の基
準電圧発生器、52……第2の基準電圧発生器、
54……第3積分ホールド回路、56……加算回
路。
FIG. 1 is a diagram showing a circuit configuration of a surveillance camera device according to an embodiment of the present invention, FIG. 2 is a diagram showing a sensing area setting method, and FIG. 3 is a time chart. 2...Camera section, 8...Monitor section, 10...
Synchronous separation circuit, 12...Window setting circuit, 2
4...First integral hold circuit, 26... Second integral hold circuit, 28... Differential amplifier, 30... Timing signal generation circuit, 38... Window comparator, 48... Notification circuit, 50... First a reference voltage generator, 52... a second reference voltage generator,
54...Third integral hold circuit, 56...Addition circuit.
Claims (1)
り映像を写し出すモニター部と、 前記カメラ部からの信号を入力して垂直同期信
号と、垂直同期信号及び水平同期信号が混合され
たコンポジツト同期信号を出力する同期分離回路
と、 この同期分離回路からの垂直同期信号とコンポ
ジツト同期信号に基づき、前記モニター部に写し
出される映像の特定領域を設定するウインドウ設
定回路と、 このウインドウ設定回路にて設定された特定領
域に対応する映像信号を積分してホールドするた
めの第1及び第2積分ホールド回路と、 この第1及び第2積分ホールド回路にてホール
ドされた値の差を出力可能な差動増幅器と、 前記同期分離回路からの垂直同期信号を分周し
かつ前記ウインドウ設定回路にて設定された特定
領域に応じて、前記第1及び第2積分ホールド回
路を数フイールド毎に交互にリセツトしてホール
ドさせる第1のタイミング信号を出力するととも
にこの第1のタイミング信号発生につづいて前記
差動増幅器を動作させる第2のタイミング信号を
出力するタイミング信号発生回路と、 第1の基準電圧を発生する第1の基準電圧発生
器と、 前記差動増幅器から出力される差電圧がこの第
1の基準電圧にて定まる電圧レンジを越えるとき
に検出信号を出力するウインドウコンパレータと
、 このウインドウコンパレータの検出信号発生に
応答して報知を行なう報知回路と、 を有する監視カメラ装置において、 第2の基準電圧を発生する第2の基準電圧発生
器と、 前記タイミング信号発生回路から第1のタイミ
ング信号に応答して前記第2の基準電圧発生器か
らの信号を積分してホールドする第3積分ホール
ド回路と、 この第3積分ホールド回路からのホールド値と
前記第1の基準信号発生器からの第1の基準電圧
を加算して前記ウインドウコンパレータに供給す
る加算回路と、 を有することを特徴とする監視カメラ装置。[Claims for Utility Model Registration] A camera unit that outputs a video signal and a synchronization signal; a monitor unit that displays an image using the video signal and synchronization signal from the camera unit; and a vertical synchronization unit that inputs signals from the camera unit. a sync separation circuit that outputs a composite sync signal that is a mixture of the signal, a vertical sync signal, and a horizontal sync signal; and a sync separation circuit that outputs a composite sync signal that is a mixture of the vertical sync signal and the horizontal sync signal; a window setting circuit for setting a region; first and second integral hold circuits for integrating and holding a video signal corresponding to the specific region set by the window setting circuit; a differential amplifier capable of outputting the difference between the values held by the hold circuit; and a differential amplifier capable of outputting the difference between the values held by the hold circuit; a second timing signal that outputs a first timing signal that resets and holds the first and second integral hold circuits alternately every several fields, and operates the differential amplifier following generation of the first timing signal; a timing signal generation circuit that outputs a first reference voltage, a first reference voltage generator that generates a first reference voltage, and a differential voltage output from the differential amplifier that exceeds a voltage range determined by the first reference voltage. A second reference voltage generator that generates a second reference voltage in a surveillance camera device comprising: a window comparator that sometimes outputs a detection signal; and an alarm circuit that issues an alarm in response to generation of the detection signal of the window comparator. a third integral hold circuit that integrates and holds the signal from the second reference voltage generator in response to the first timing signal from the timing signal generating circuit; A surveillance camera device comprising: an addition circuit that adds a hold value and a first reference voltage from the first reference signal generator and supplies the result to the window comparator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6292989U JPH032786U (en) | 1989-05-30 | 1989-05-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6292989U JPH032786U (en) | 1989-05-30 | 1989-05-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH032786U true JPH032786U (en) | 1991-01-11 |
Family
ID=31592523
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6292989U Pending JPH032786U (en) | 1989-05-30 | 1989-05-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH032786U (en) |
-
1989
- 1989-05-30 JP JP6292989U patent/JPH032786U/ja active Pending
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