JPH033893U

JPH033893U -

Info

Publication number: JPH033893U
Application number: JP6351189U
Authority: JP
Priority date: 1989-05-31
Filing date: 1989-05-31
Publication date: 1991-01-16

Description

[Brief explanation of drawings]

第１図は本考案の一実施例に係る監視カメラ装
置の回路構成を示す図、第２図はタイムチヤート
である。２……カメラ部、８……モニター部、１０……
同期分離回路、１２……ウインドウ設定回路、２
０……第１積分ホールド回路、２２……第２積分
ホールド回路、２４……差動増幅器、２６……タ
イミング信号発生回路、３４……ウインドウコン
パレータ、４４……報知回路、４６……第１の基
準電圧発生器、４８……第２の基準電圧発生器、
５０……コンパレータ、５２……第３積分ホール
ド回路、５４……加算回路。 FIG. 1 is a diagram showing a circuit configuration of a surveillance camera device according to an embodiment of the present invention, and FIG. 2 is a time chart. 2...Camera section, 8...Monitor section, 10...
Synchronous separation circuit, 12...Window setting circuit, 2
0...First integral hold circuit, 22...Second integral hold circuit, 24...Differential amplifier, 26...Timing signal generation circuit, 34...Window comparator, 44...Notification circuit, 46...First a reference voltage generator, 48... a second reference voltage generator,
50...Comparator, 52...Third integral hold circuit, 54...Addition circuit.

Claims

[Claims for Utility Model Registration] A camera unit that outputs a video signal and a synchronization signal; a monitor unit that displays an image using the video signal and synchronization signal from the camera unit; and a vertical synchronization unit that inputs signals from the camera unit. a sync separation circuit that outputs a composite sync signal that is a mixture of the signal, a vertical sync signal, and a horizontal sync signal; and a sync separation circuit that outputs a composite sync signal that is a mixture of the vertical sync signal and the horizontal sync signal; a window setting circuit for setting a region; first and second integral hold circuits for integrating and holding a video signal corresponding to the specific region set by the window setting circuit; A differential amplifier capable of outputting the difference between the values held in the hold circuit; and a vertical synchronization signal from the synchronization separation circuit are frequency-divided to alternately operate the first and second integral hold circuits every several fields. A first timing signal to be reset and held is outputted, and this first timing signal is reset and held.
a timing signal generation circuit that outputs a second timing signal that operates the differential amplifier following generation of the timing signal; a first reference voltage generator that generates a first reference voltage; and a first reference voltage generator that generates a first reference voltage from the differential amplifier. A window comparator that outputs a detection signal when the output differential voltage exceeds a voltage range determined by the first reference voltage, and a notification circuit that provides notification in response to generation of the detection signal of the window comparator. In the surveillance camera device, a second reference voltage generator that generates a second reference voltage compares the video signal from the camera section with the second reference voltage, and outputs the signal when the video signal level is high. a comparator to output, and an output voltage value from this comparator to the first
a third integral hold circuit that integrates and holds in response to a timing signal; an adder circuit that adds the hold value from the third integral hold circuit and the first reference voltage and supplies the result to the window comparator; A surveillance camera device comprising: