JPH03280429A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH03280429A
JPH03280429A JP7990690A JP7990690A JPH03280429A JP H03280429 A JPH03280429 A JP H03280429A JP 7990690 A JP7990690 A JP 7990690A JP 7990690 A JP7990690 A JP 7990690A JP H03280429 A JPH03280429 A JP H03280429A
Authority
JP
Japan
Prior art keywords
film
insulating film
cvd
oxide film
oxidation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7990690A
Other languages
Japanese (ja)
Inventor
Hiroki Tsuruta
鶴田 浩己
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP7990690A priority Critical patent/JPH03280429A/en
Publication of JPH03280429A publication Critical patent/JPH03280429A/en
Pending legal-status Critical Current

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  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To avoid the occurrence of bird's beak during the selective oxidation process by a method wherein the second oxidation resistant insulating film is deposited on the whole surface of the first insulating film having an opening part on a semiconductor substrate, a coated film at almost the same etching rate is formed leaving the second insulating film only in the opening part by the whole surface etching process to be selectively oxidized for element isolation. CONSTITUTION:A CVD oxide film 11 as the first insulating film is deposited on a semiconductor substrate 10 further exposed and developed for patterning to make an opening part. Next, after depositing a CVD nitride film 13 as the second insulating film, a coated film 14 at almost the same etching rate is deposited, the surface is flattened and etched away until the nitride film 13 on the CVD oxide film 11' disappears and then the coated film 14' and the CVD oxide film 11' are removed by wet etching process. Next, the whole surface is selectively oxidized to form a field oxide film 16 after ion implantation for preventing the interelement parasitic channel using the CVD nitride film 13' as a mask. Finally, the CVD nitride film 13' is wet-etched to finish the element isolation.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置の製造方法、特にLSIにおける
素子分離技術に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and in particular to an element isolation technique in an LSI.

〔従来の技術〕[Conventional technology]

LSI製造技術として、窒化膜をマスクとして選択酸化
による厚い酸化膜を用いる、素子分離技術は周知である
。第2図を参照してこの技術につき説明する。同図(a
)に示すように、半導体基板l上に熱酸化膜2と、CV
D窒化膜3を堆積させる。熱酸化W22は後でCVD窒
化膜3をパターニングするドライエツチング時の応力を
防ぐ緩和材となっている0次に同図(b)に示すように
、予定する素子領域の部位において、ホトレジスト4を
マスクとして、素子分離領域のCVD窒化膜を除去した
後、イオン注入を行なう、イオン注入は素子間寄性チャ
ネル防止のためで、NチャネルMOSトランジスタの場
合は、ホウ素イオン5を用いる0次に同図(C)に示す
ようにホトレジスト4を除去してから、例えば!000
℃、H7−02ふんい気中で酸化を行なう。CVD窒化
W23は耐酸化性が強く酸化に対するマスクになり、素
子領域を除く部分だけが厚く酸化され、フィールド酸化
膜6を形成する0次に、下地の薄い熱酸化W22を除去
すると、同図(d)に示すように、素子分離が完了する
As an LSI manufacturing technique, an element isolation technique using a thick oxide film by selective oxidation using a nitride film as a mask is well known. This technique will be explained with reference to FIG. The same figure (a
), a thermal oxide film 2 and a CV
Deposit D nitride film 3. Thermal oxidation W22 acts as a relaxing material to prevent stress during dry etching for patterning the CVD nitride film 3. Next, as shown in FIG. After removing the CVD nitride film in the element isolation region as a mask, ion implantation is performed to prevent parasitic channels between elements. After removing the photoresist 4 as shown in Figure (C), for example! 000
Oxidation is carried out at 0.degree. C. in H7-02 atmosphere. The CVD nitrided W23 has strong oxidation resistance and acts as a mask against oxidation, and is thickly oxidized only in the area excluding the element area, forming the field oxide film 6. Next, when the thin underlying thermally oxidized W22 is removed, the same figure ( As shown in d), element isolation is completed.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上記の従来の素子分離方法では、耐酸化性マスクの窒化
膜の下地の熱酸化膜(パッド酸化膜)は、フィールド酸
化のとき横方向にも酸化が進行し、バーズビーク(bi
rd’s beak)状の酸化膜が形成され、素子領域
幅がマスク寸法と異なるという欠点があった。また高集
積化の制限になっていた。
In the conventional device isolation method described above, the thermal oxide film (pad oxide film) underlying the nitride film of the oxidation-resistant mask is oxidized in the lateral direction during field oxidation, resulting in bird's beaks.
There was a drawback that an oxide film was formed in the shape of a rd's beak, and the width of the element region was different from the mask dimension. It also became a restriction on high integration.

本発明の目的は、上記の欠点を除去した、半導体装置の
製造方法を提供することにある。
An object of the present invention is to provide a method for manufacturing a semiconductor device that eliminates the above-mentioned drawbacks.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体装置の製造方法は、半導体基板上に、素
子領域の予定部位に、開口を有する第1絶縁膜を形成す
る工程と2次に耐酸化性の第2絶縁膜を全面に成長させ
る工程と、前記第2絶縁膜上に第2絶縁膜と同程度のエ
ツチングレートなもつ塗布膜を成膜し表面を平坦化する
工程と9次に全面エツチングにより前記開口部にのみ第
2絶縁膜を残す工程と、前記第2絶縁膜により選択酸化
を行なう工程とによって素子分離を行なう。
The method for manufacturing a semiconductor device of the present invention includes a step of forming a first insulating film having an opening on a semiconductor substrate at a predetermined location of an element region, and then growing an oxidation-resistant second insulating film over the entire surface. a step of forming a coating film having an etching rate similar to that of the second insulating film on the second insulating film and flattening the surface; and a ninth step of forming a second insulating film only in the opening by etching the entire surface Element isolation is performed by a step of leaving the oxide film and a step of performing selective oxidation using the second insulating film.

〔作用〕[Effect]

本発明では、素子領域の予定部位に、Im!化性の絶縁
膜によるマスクを作成する場合に、ドライエツチングを
しないので、ドライエツチングの際の損傷をふせぐスト
ッパの役をするパッド酸化膜を必要としない、したがっ
て、選択酸化ノ際にバーズビークの発生がない。
In the present invention, Im! When creating a mask using a oxidizing insulating film, dry etching is not performed, so there is no need for a pad oxide film that acts as a stopper to prevent damage during dry etching.Therefore, bird's beaks do not occur during selective oxidation. There is no.

〔実施例〕〔Example〕

以下、図面を参照して、本発明の一実施例につき説明す
る。第1図は第1実施例を工程順に示した縦断面図であ
る。同図(a、 )に示すように、半導体基板10上に
第1絶縁膜としてCVD酸化17911を堆積させる。
Hereinafter, one embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a vertical sectional view showing the first embodiment in the order of steps. As shown in FIG. 4A, CVD oxidation 17911 is deposited on the semiconductor substrate 10 as a first insulating film.

そして、ホトレジスト12を塗布後、露光・現像を行な
い素子領域上のみホトレジストが無いようにパターニン
グして開口する。同図(b)に示すように、第2絶縁膜
としてCVD窒化[13を堆積後、窒化膜と同じ程度の
ニー、チングレートを持つ塗布膜14を堆積させ、表面
を平坦にする。
After coating the photoresist 12, exposure and development are performed to pattern and open only the element region so that there is no photoresist. As shown in FIG. 4B, after CVD nitride film 13 is deposited as a second insulating film, a coating film 14 having a knee and ting rate similar to that of the nitride film is deposited to flatten the surface.

次に、同図(C)に示すように、反応性イオンエツチン
グによりCVD酸化[11’上の窒化膜が無くなるまで
エツチングを行なってがら、塗布mx 、a’ とCv
ps化11111′ヲウエー7トエルチングで除去する
。その後で同図(d)に示すように、CVD窒化膜13
′をマスクにして、素子間寄生チャネル防止用にイオン
注入(Nチャネルの場合ホウ素イオン15)後、例えば
1000℃、H2−07,雰囲気で選択酸化を行ない、
フィールド酸化膜16を形成する。最後に同図(e)に
示すように、CVD窒化膜13’をウェー2トエツチン
グすることにより素子分離が完了する8 半導体基板が高儂度の不純物をドーピングされている場
合には、第1実施例の場合と異なり、チャネル防止用イ
オン注入が不必要なので、第1図(c)におけるCVD
酸化j!II 1’は除去せずフィールド酸化を行なう
、この例では所望の厚さのフィールド酸化膜厚を得るた
めの選択酸化の程度は少なくてすむので、選択酸化の際
の応力の影響は少ない。
Next, as shown in the same figure (C), while performing reactive ion etching until the nitride film on the CVD oxide [11' is removed], the coating mx, a' and Cv are etched.
PS 11111' is removed by 7-torching. After that, as shown in the same figure (d), the CVD nitride film 13 is
′ as a mask, after ion implantation (15 boron ions in the case of N channel) to prevent parasitic channels between elements, selective oxidation is performed at 1000° C. in H2-07 atmosphere, for example.
A field oxide film 16 is formed. Finally, as shown in FIG. 2(e), device isolation is completed by weight-etching the CVD nitride film 13'.8 If the semiconductor substrate is doped with a high degree of impurity, Unlike the case in the example, ion implantation for channel prevention is unnecessary, so the CVD method in Fig. 1(c)
Oxidation j! In this example, where II1' is not removed but field oxidized, the degree of selective oxidation required to obtain a desired field oxide film thickness is small, so that the influence of stress during selective oxidation is small.

〔発明の効果〕〔Effect of the invention〕

選択酸化分離方法では、素子領域の予定部位に、耐酸化
性絶縁膜を形成して選択酸化を行なうが、従来は耐酸化
性絶縁膜の下部に薄い酸化膜があるので、選択酸化の際
にバーズビークが発生していた。しかし、本発明では素
子領域に耐酸化性絶縁膜(第2絶縁膜)のパターンを形
成する工程は、第1絶縁膜の開口部に、基板に直接に接
してIFl酸化性絶縁膜が残るような方法で行なう。し
たがって、耐酸化性絶縁膜の下部には酸化膜がなく、選
択酸化に際し、バーズビークは生じない。
In the selective oxidation isolation method, selective oxidation is performed by forming an oxidation-resistant insulating film at the intended location of the element region. Conventionally, there is a thin oxide film under the oxidation-resistant insulating film, A bird's beak was occurring. However, in the present invention, the step of forming the pattern of the oxidation-resistant insulating film (second insulating film) in the element region is performed so that the IFL oxidizing insulating film remains in the opening of the first insulating film in direct contact with the substrate. Do it in a certain way. Therefore, there is no oxide film under the oxidation-resistant insulating film, and bird's beaks do not occur during selective oxidation.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示す縦断面図、第2図は従
来例の縦断面図である。 10・・・半導体基板、 11 、11’・・・CVD1’l化膜(笛 t  h
& kn W5 ) 13.13’・・・CVD窒化膜 (第2絶縁M) 14.14’・・・塗布膜、 15・・・ホウ素イオン、 16・・・フィールド酸化膜。 特 許 出 願 人 日本電気株式会社
FIG. 1 is a vertical cross-sectional view showing one embodiment of the present invention, and FIG. 2 is a vertical cross-sectional view of a conventional example. 10... Semiconductor substrate, 11, 11'... CVD 1'l film (whistle th
& kn W5) 13.13'...CVD nitride film (second insulation M) 14.14'...Coating film, 15...Boron ion, 16...Field oxide film. Patent applicant NEC Corporation

Claims (1)

【特許請求の範囲】[Claims]  半導体基板上に、素子領域の予定部位に、開口を有す
る第1絶縁膜を形成する工程と、次に耐酸化性の第2絶
縁膜を全面に成長させる工程と、前記第2絶縁膜上に第
2絶縁膜と同程度のエッチングレートをもつ塗布膜を成
膜し表面を平坦化する工程と、次に全面エッチングによ
り前記開口部にのみ第2絶縁膜を残す工程と、前記第2
絶縁膜により選択酸化を行なう工程を含み、素子分離を
行なうことを特徴とする、半導体装置の製造方法。
a step of forming a first insulating film having an opening on a semiconductor substrate at a predetermined location of an element region; a step of growing an oxidation-resistant second insulating film over the entire surface; a step of forming a coating film having an etching rate similar to that of the second insulating film and flattening the surface; a step of leaving the second insulating film only in the opening by etching the entire surface;
1. A method of manufacturing a semiconductor device, which includes a step of performing selective oxidation using an insulating film to perform element isolation.
JP7990690A 1990-03-28 1990-03-28 Manufacture of semiconductor device Pending JPH03280429A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7990690A JPH03280429A (en) 1990-03-28 1990-03-28 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7990690A JPH03280429A (en) 1990-03-28 1990-03-28 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH03280429A true JPH03280429A (en) 1991-12-11

Family

ID=13703327

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7990690A Pending JPH03280429A (en) 1990-03-28 1990-03-28 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH03280429A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5654227A (en) * 1996-01-23 1997-08-05 Micron Technology, Inc. Method for local oxidation of silicon (LOCOS) field isolation
KR19980048151A (en) * 1996-12-17 1998-09-15 문정환 Separator Formation Method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5654227A (en) * 1996-01-23 1997-08-05 Micron Technology, Inc. Method for local oxidation of silicon (LOCOS) field isolation
US6090727A (en) * 1996-01-23 2000-07-18 Micron Technology, Inc. Method for local oxidation of silicon (LOCOS) field isolation
KR19980048151A (en) * 1996-12-17 1998-09-15 문정환 Separator Formation Method

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