JPH03280442A - semiconductor equipment - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device in which a plurality of inner leads are directly bonded by thermocompression bonding with an adhesive onto the circuit element forming surface of a semiconductor chip. It relates to techniques that can be applied and are effective.

[Conventional technology]

Semiconductor devices are sealed with mold resin to protect semiconductor chips. In this semiconductor device, several methods are used to position and attach leads on the semiconductor chip before the semiconductor chip is sealed with a molding resin.

For example, a plurality of inner leads are bonded with an adhesive on the circuit element forming surface of a semiconductor chip with an insulating film that is electrically insulated from the semiconductor chip interposed, and the semiconductor chip and the inner leads are connected to each other using a bonding wire. The so-called L O is connected to the
A semiconductor device having a G (Lead On Chi ρ) structure has been proposed (see Japanese Patent Laid-Open No. 61-241959).

[Problem to be solved by the invention]

However, as a result of studying the semiconductor device, the inventor found the following problems.

In the semiconductor device, a plurality of inner leads are disposed on the circuit element forming surface of the semiconductor chip with an insulating film interposed therebetween, and bonding wires are crimped and connected to the bonding surface of the inner leads, so that the circuit of the semiconductor chip is There is a problem in that an impact load or a pressure load is applied to the element forming surface, damaging the circuit element forming surface (the element of the semiconductor chip) of the semiconductor chip, and reducing the reliability of the semiconductor device.

An object of the present invention is to provide a technique that can improve the reliability of a semiconductor device having a LOG structure.

Another object of the present invention is to provide a technique capable of reducing the size of a semiconductor chip and package of a semiconductor device having an LOG structure.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief summary of typical inventions disclosed in this application is as follows.

(1) A plurality of inner leads are bonded by thermocompression on the circuit element forming surface of the semiconductor chip through an adhesive, a bonding pad hole is provided on the protective film of the semiconductor chip, and an external A terminal is provided, the tip of the inner lead is thinner than the inner lead body, and the tip of the inner lead and the external terminal of the bonding pad hole of the semiconductor chip are connected by a vapor-deposited metal film. This is a semiconductor device that is electrically connected, a protective film for preventing alpha rays from entering is provided on at least the connecting portion, and is sealed with a molding resin.

(2) Instead of making the tip of the inner lead thinner than the lead body, the tip of the inner lead is provided with a bowl-shaped hole and a through hole in the center thereof.

(3) On the protective film of the semiconductor chip, a plurality of printed signal wirings, printed external terminals, and a printed common wiring stretched in parallel to the long sides of the protective film are provided at the center of the protective film. be.

[For production]

According to the above-mentioned means (1), a plurality of inner leads are arranged on the circuit element forming surface of the semiconductor chip via an insulating film, and a bonding pad hole is provided on the protective film of the semiconductor chip. , the tip portion of the inner lead is configured to be thinner than the inner lead body, and the tip portion of the inner lead and the external terminal of the bonding pad hole of the semiconductor chip are electrically connected by a vapor-deposited metal film. As a result, the stress applied to the circuit element forming surface can be reduced, so that damage to the circuit element can be reduced. Thereby, the reliability of the semiconductor device having the LOG structure can be improved.

According to the above-mentioned means (2), instead of making the tip of the inner lead thinner than the lead body, a bowl-shaped hole is provided at the tip of the inner lead and a through hole is formed in the center of the hole. By providing this, it is possible to reduce the stress applied to the circuit element formation surface, and also to easily connect with a vapor-deposited metal film, thereby reducing damage to the circuit element.

According to the above-mentioned means (3), on the protective film of the semiconductor chip, there are a plurality of printed signal wirings, printed external terminals, and printed common terminals extending parallel to the long sides of the protective film at the central part thereof. By providing wiring, even if the wiring inside the semiconductor chip is thin, the printed signal line (inner lead) can be made thicker on the protective film (passivation film), reducing the resistance value of the operating current path. can do. This makes it possible to improve the operating speed.

Furthermore, since there is an increased degree of freedom in where printed signal wiring and printed external terminals are provided on the protective film, it is possible to connect to a power source from anywhere. This makes it possible to supply current with short wiring, thereby reducing the resistance value and reducing noise.

Further, since the positions of the printed external terminals on the semiconductor chip can be changed on the protective film, the size of the semiconductor chip and package can be reduced.

In addition, on the protective film, there is more freedom in the location of printed signal wiring and printed external terminals, and the position of the printed external terminals on the semiconductor chip can be changed, so there is freedom in package design for LOG structure semiconductor devices. degree can be increased.

Further, since the central portion of the semiconductor chip is provided with printed common wiring extending parallel to its long sides, it can be connected to a power source from one of various locations.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of the present invention will be described below along with an embodiment in which the present invention is applied to a resin-sealed semiconductor device in which a DRAM (semiconductor chip) is sealed with a mold resin.

In addition, in all the times for explaining the example.

Components having the same function are given the same reference numerals, and repeated explanations thereof will be omitted.

[Example ■]

1 (partial cross-sectional perspective view), FIG. 2 (plan view), and FIG. 3 (cross section taken along line E in FIG. Figure).

As shown in FIG. 1, FIG. 2, and FIG. 3, the semiconductor chip 1 of the present embodiment
1ine J-bend) type resin sealed package 2
is sealed with. The semiconductor chip 1 is 1, for example 16
[Mbit] X 1 [bit] large capacity DR
A M (Dynamic Random Accesses)
s Memory), 16°48[mml
It is composed of a rectangular planar shape of X8.54 [mml]. This semiconductor chip 1 is sealed in a resin-sealed package 2 of 400 [mil].

Although not shown, a memory cell array and peripheral circuits are mainly arranged on the circuit element formation surface (hereinafter referred to as the main surface) of the semiconductor chip (DRAM) 1. The memory cell array consists of memory cells (
A plurality of memory elements (memory elements) are arranged in a matrix. The peripheral circuit includes a direct peripheral circuit and an indirect peripheral circuit.

The direct peripheral circuit is a circuit that directly controls the information write operation and information read operation of the memory cell. The direct peripheral circuit is
It includes a row address decoder circuit, a column address decoder circuit, a sense amplifier circuit, etc. The indirect peripheral circuit is a circuit that indirectly controls the operation of the direct peripheral circuit.The indirect peripheral circuit includes a clock signal generation circuit, a buffer circuit, and the like.

On the opposing side end surfaces of the rectangular semiconductor chip 1,
The support lead 3C is fixed with an adhesive. This support lead 3c is the inner lead 3 of the semiconductor chip.
It is bent downward from the plane where A is placed.

However, one end of the inner lead 3A is integrally formed with the outer lead 3B. The signals applied to each outer lead 3B are defined and numbered based on standards. In FIG. 1, the terminal on the left is terminal No. 1, and the terminal on the right is terminal No. 14. The rear right end (the terminal numbers are shown in FIG. 2) is the 15th terminal, and the rear left end (the terminal numbers are shown in FIG. 2) is the 28th terminal. In other words, this resin-sealed package 2 has terminals 1 to 6 and terminals 9 to 14.

It is composed of a total of 24 terminals, including terminals 15 to 20 and terminals 23 to 28.

The first terminal is a power supply voltage Vcc terminal. The power supply voltage Vcc is, for example, a circuit operating voltage of 5 [V]. The 2nd terminal is a data signal terminal (D), the 3rd terminal is an empty terminal, the 4th terminal is a write enable signal terminal (W), 5#i
The terminal is a row address strobe signal terminal (RE), and the sixth terminal is an address signal terminal (A□□).

The 9th terminal is the address signal terminal (A□.), the 10th terminal is the address signal terminal (A,), the 111th terminal is the address signal terminal (A1), and the 12th terminal is the address signal terminal (A2).
, the 13th terminal is the address signal terminal (A3), 14
The number terminal is the power supply voltage Vcc terminal.

Although not shown in Figure 1, terminal 15 is connected to the reference voltage V.
This is the ss terminal. The reference voltage Vss is, for example, a circuit reference voltage of 0 [V]. The 16th terminal is the address signal terminal (A,), the 17th terminal is the address signal terminal (A,), 1
The 8th terminal is an address signal terminal (A, ), the 19th terminal is an address signal terminal (A1), and the 20th terminal is an address signal terminal (A8).

Although not shown in Figure 1, the 23rd terminal is an address signal terminal (A,), the 24th terminal is an empty terminal, the 25th terminal is a column address strobe signal terminal (CE), and 26##
The terminal is an empty terminal, the 27th terminal is a data output signal terminal, 2
The No. 8 terminal is a reference voltage Vss terminal.

The other end side of the inner lead 3A crosses each long side of the rectangular shape of the semiconductor chip 1 and is extended toward the center of the semiconductor chip 1.

The inner leads (Vcc) 3A of the 1st terminal and the 14th terminal among the inner leads 3A are electrically connected to the printed common wiring 3AC. Similarly, the inner leads (Vss) 3A of the 15th terminal and the 28th terminal are electrically connected to the printed common wiring 3AC.

Inner lead of terminal 1 and terminal 14 (Vcc) 3
A, Inner lead of terminal 15 and terminal 28 (Vs
s) Each of 3A is connected to other inner leads 3A(
They are made to coexist in parallel within a region defined by the tip of the other end of the signal inner lead 3A). Inner leads (Vcc) of this No. 1 and No. 14 terminals 3A, 15
Inner lead (Vss) of terminal No. 2 and No. 28 terminal 3A
are configured so that the power supply voltage Vcc and the reference voltage Vss can be supplied to any position on the main surface of the semiconductor chip 1. In other words, this resin-sealed semiconductor device is configured to easily absorb power supply noise, and is configured to increase the operating speed of the semiconductor chip 1.

The inner lead 3A, outer lead 3B, and support lead 3c are each cut from the lead frame and molded.

The semiconductor chip 1, inner leads 3A, and support leads 3C are sealed with a molding resin 2A. This mold resin 2A uses an epoxy resin to which a phenolic curing agent, silicone rubber, and filler are added in order to reduce stress. Silicone rubber has the effect of lowering the elastic modulus and thermal expansion coefficient of the epoxy resin. The filler is made of spherical silicon oxide particles, and similarly has the effect of lowering the coefficient of thermal expansion. Furthermore, an index ID (notch provided at the left end in FIGS. 1 and 2) is provided at a predetermined position on the package 2.

A passivation film (protective film) 102 is formed on the main surface of the semiconductor chip 1, as shown in FIG. 4 (an enlarged sectional view of the connection between the inner lead and the single conductor chip). The main surface of this passivation film 102 is coated using printed wiring technology.

01J print common wiring 3AC1 print bonding pad BP and a plurality of print signal distribution M3AP integrally formed with the print bonding pad BP are formed. The printed common wiring 3AC and the plurality of printed signal wiring AI+83AP are connected to the connection holes 10 formed in the passivation film 102.
3 and is electrically connected to the internal wiring 104.

On the main surface of the semiconductor chip 1 including the printed common wiring 3AC and the plurality of printed signal wirings 3AP, a 10 μm film made of polyimide resin is coated to prevent α rays from entering.
A protective film 105 for preventing intrusion of alpha rays with a thickness of about 7'i is coated. The α-ray intrusion prevention protective film 105 has a bonding pad hole 106 formed by dry etching according to a predetermined mask pattern, and the surface of the bonding pad (external terminal) BP is exposed to mist.

The printed signal wiring 3AP, printed bonding pad BP
And the printed common wiring 3AC is made of, for example, a Ti film 301 with a thickness of about 0.2 μm, and a Cυ film 30 with a thickness of about 2 μm.
A multilayer wiring made of a Ti film 303 with a thickness of about 2 and 0.2 μm is used. This multilayer wiring may be an aluminum (Al) or gold (Au) wire. That is, the active area (not shown) of the semiconductor chip 1, the printed signal wiring 3AP, the printed bonding pad I3P, and the printed common wiring 3AC are connected to the connection hole 103 and the internal wiring 104.
electrically connected through.

Further, the circuit element formation layout of the semiconductor chip 1 is shown in FIG. 5 (circuit element formation layout diagram of the semiconductor chip).
In FIG. 5, 11 is a memory cell array;
2 is a peripheral circuit, and BP is a printing pad.

A plurality of inner leads 3A are disposed on the main surface of the semiconductor chip 1, that is, the surface on which the memory cell array 11 and the peripheral circuit 12 are arranged, and on the main surface of the passivation film 102 of the semiconductor chip 1, a printing layer is formed. Signal wiring 3
AP, printing bonding bat BP and printing common wiring 3
AC is formed.

As shown in FIGS. 4 and 6A, the tip portions 3A of the inner leads 3A are configured to have a thickness smaller than that of the inner lead bodies, and are heated on the main surface of the passivation film 102 of the semiconductor chip 1. They are directly bonded by thermocompression using an adhesive 4 such as plastic polyimide.

The printed bonding pad BP of the semiconductor chip 1 and the tip portion 3A□ of the inner lead 3A are electrically connected.

The electrical connection between the printed bonding pads BP of the semiconductor chip 1 and the tip portions 3A1 of the inner leads 3A is as shown in FIG. 6B. Next, as shown in FIG. The deposited film 107 is photo-etched to form a predetermined aluminum (A1) deposited film pattern 108. As shown in FIG. 6D, at least on the aluminum (Al) vapor deposited film pattern 108, an α-ray intrusion prevention film made of polyimide resin and having a thickness of about 10 μm is provided to prevent α-ray intrusion. A protective film 105 is coated.

As shown in FIGS. 1 and 7 (plan view of the entire lead frame), the lead frame is composed of 20 inner leads 3A (for signals) and support leads (hanging leads) 3C. This lead frame 3 is, for example, F'e
-Ni (for example, N1 content 42 or 50%) alloy,
It is made of Cu or the like.

This type of resin-sealed package 2 is a LOC (Le
Ad On Chip) structure is adopted.

The resin-sealed package 2 that adopts the LOG structure allows the inner leads 3A to be routed freely without being restricted by the shape of the semiconductor chip 1, so the larger semiconductor chip 1 can be sealed by the amount corresponding to this route. be able to.

In other words, resin-sealed package 2 that uses LOCi construction.
Even if the size of the semiconductor chip 1 increases due to the increase in capacity, the sealing size (package size) can be kept small, so the packaging density can be increased.

Support leads 3C are connected and fixed to opposing side ends of the main surface of the rectangular semiconductor chip 1 with an adhesive 5. As the adhesive, an adhesive such as an epoxy resin or a resol resin is used.

Note that the support leads 3C and the semiconductor chip 1 are preferably fixed by adhesive at the opposing side ends of the main surface of the rectangular semiconductor chip 1 as described above, but if necessary, It may be fixed on the back side.

As can be seen from the above description, according to the present embodiment (2), as shown in FIGS. 4 and 6A to 6D, the tips 3A of the inner leads 3A are
1 is thermocompression bonded with adhesive 4, and this tip 3A1
and a printed bonding pad BP of the semiconductor chip 1.
By electrically connecting the aluminum membrane film (vapor deposited film) 108, the stress applied to the main surface can be reduced, so that damage to the circuit elements on the main surface can be reduced during bonding. can. This allows LOG
The reliability of the semiconductor device structure can be improved.

In addition, the passivation film (protective film) of the semiconductor chip 1
On the main surface of 102, a plurality of printed signal wirings 3AP, printed bonding pads BP and their passivation films 10
Since the common printing pattern M3AC is provided in the central part on the main surface of the semiconductor chip 1 and extends parallel to its long side, even if the internal wiring 104 of the semiconductor chip 1 is thin, it can be easily printed on the main surface of the passivation film 102. Since the printed signal wiring (inner lead) 3AP can be made thicker, the resistance value of the operating current path can be reduced. This makes it possible to improve the operating speed.

Further, since there is an increased degree of freedom regarding the location on the main surface of the passivation film 102 where the printed signal wiring 3AP and the printed bonding pad BP are provided, it is possible to connect to the power source from anywhere. This makes it possible to supply current with short wiring, thereby reducing the resistance value and reducing noise.

Furthermore, since the position of the printing pad BP can be changed on the main surface of the passivation film 102,
The size of the semiconductor chip 1 and the package can be reduced.

Further, on the main surface of the passivation film 102, the degree of freedom is increased regarding the location where the printed signal wiring 3AP and the printed bonding pad BP are provided, and the position of the printed bonding pad BP can be changed. The degree of freedom in device package design can be increased.

Furthermore, since the printed common wiring 3Ac is provided extending parallel to the long sides of the central portion of the semiconductor chip 1, it is possible to connect to the power source from various locations.

[Example ■]

FIG. 8 is a partial cross-sectional perspective view showing the schematic structure of a semiconductor device according to Example 2 of the present invention, and FIG. 9A (plan view) and FIG. 9B (Rollo line sectional view of FIG. 9A) are Figures showing the configuration of the tip, Figures 10A, 10B, 10
Figure C and Figure 10D are explanatory diagrams for explaining the configuration of the electrical connection portion between the inner lead and the semiconductor chip;
The figure is a diagram showing the overall structure of a lead frame of Example H.

The semiconductor device of Example H is shown in FIGS. 8 and 9A.

As shown in FIGS. 9B and 11, instead of making the tip portion 3A□ of the inner lead 3A of the first embodiment thinner than the thickness of the inner lead body, a bowl-shaped hole and a through hole 3A are formed in the center thereof. , is provided. In other words,
The area around the through hole 3A2.

As shown in FIGS. 9A and 9B, a bowl-shaped hole 3A3 having a diameter of about 0.3 layers is formed.

The electrical connection between the printed bonding pad BP of the semiconductor chip 1 and the tip of the inner lead 3A is made through the first
As shown in Fig. 0A, first, the semiconductor chip 1 is bonded by thermocompression directly onto the main surface of a passivation film (not shown) using an adhesive 4 such as thermoplastic polyimide, as shown in Fig. 10B. As shown, aluminum (Al) or other highly conductive metal is vapor-deposited using a mask 110 on the printed bonding bat BP of the semiconductor chip 1, the through hole 3 Az at the tip of the inner lead 3A, and the bowl-shaped hole 3A3. A film 108 is deposited.

As shown in FIG. 10C, at least the above-mentioned through hole 3A2 and the bowl-shaped hole 3A3 are made of polyimide resin to prevent α rays from entering and have a diameter of about 10 μm. A protective protective film 105 is coated.

As can be seen from the above description, according to the present embodiment (2), instead of configuring the Iq of the tip portion 3A of the inner lead 3A to be thinner than the inner lead body, the tip portion of the inner lead 3A has a bowl shape. By providing the hole 3A and the through hole 3A in the center thereof, it is possible to reduce the stress applied to the circuit element formation surface, and to easily connect with the vapor-deposited metal film, reducing damage to the circuit element. can do.

The present invention has been specifically described above based on examples.
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

Since damage to the main surface of the semiconductor chip can be reduced, the reliability of the LOG structure semiconductor device can be improved.

Furthermore, since the resistance value of the operating current path can be reduced, the operating speed can be improved.

In addition, since it can be connected to a power source from anywhere, current can be supplied with short wiring, making it possible to reduce resistance, increase speed, and reduce noise.

Further, since the position of printed external terminals (printed bonding pads) on the semiconductor chip can be changed on the protective film, the size of the semiconductor chip and package can be reduced.

Further, since the position of the printed external terminal can be changed on the protective film, the degree of freedom in designing the package of the semiconductor device having the LOG structure can be increased.

Further, since the printed common wiring is provided on the long side of the central portion of the protective film and extends in parallel, it is possible to connect to the power source from various locations.

[Brief explanation of the drawing]

Figure 1 is an example of the present invention! FIG. 2 is a plan view of FIG. 1, FIG. 3 is a sectional view taken along line E in FIG. 2, and FIG. FIG. 5 is an enlarged sectional view of the connecting portion between the inner lead and the semiconductor chip, and FIG. 5 is a layout diagram of the circuit element formation of the semiconductor chip. Figures 6A, 6B, 6C, and 6D. FIG. 3 is a diagram for explaining a process of forming a connection portion between an inner lead and a semiconductor chip. FIG. 7 is an overall plan view of a lead frame of Example I, FIG. 8 is a partial cross-sectional perspective view showing a schematic configuration of a resin-sealed semiconductor device according to Example 2 of the present invention, and FIG. 9A is a A plan view showing the configuration of the tip of the inner lead, FIG. 9B is a sectional view taken along the Rolo line in FIG. 9A, FIGS. 10A, 10B, 10C, and 10D are
FIG. 11 is an overall plan view of the lead frame of Example H. In the figure, 1... semiconductor chip (DRAM), 2... resin-sealed package, 3... lead frame, 3A...
・Inner lead, 3B...Outer lead, 3C・
・・Support lead, 3AC・・Printed common wiring, 3AP・
・・Printed signal wiring, BP・・Printed bonding pad (
Printed external terminal), 4... Adhesive, 11... Memory cell array, 12... Peripheral circuit, 102... Passivation film, 103... Connection hole, 104... Internal wiring, 105...・Protective film for preventing alpha rays from entering, 105A...
- Bonding hole, 108... Aluminum vapor deposited film.

Claims (1)

[Claims] 1. A plurality of inner leads are directly bonded with an adhesive onto the circuit element forming surface of the semiconductor chip, external terminals are provided on the protective film of the semiconductor chip, and the tip portions of the inner leads are provided with external terminals on the protective film of the semiconductor chip. The thickness of the inner lead is thinner than that of the inner lead body, the tip of the inner lead and the external terminal of the semiconductor chip are electrically connected by a vapor-deposited metal film, and a film for preventing alpha rays from entering is formed on at least the connection part. A protective film is provided,
A semiconductor device characterized by being sealed with mold resin. 2. A plurality of inner leads are bonded directly to the circuit element formation surface of the semiconductor chip via an adhesive, external terminals are provided on the protective film of the semiconductor chip, and a bowl-shaped shape is provided at the tip of the inner lead. A through hole is provided in the hole and its center, and the tip of the inner lead and the external terminal of the semiconductor chip are electrically connected through the through hole by a vapor-deposited metal film, and at least on the connecting portion. A semiconductor device characterized by being provided with a protective film for preventing intrusion of alpha rays and sealed with mold resin. 3. The semiconductor device according to claim 1 or 2,
a plurality of printed signal wirings on the protective film of the semiconductor chip;
1. A semiconductor device comprising a printed external terminal and a printed shared wiring extending parallel to the long sides of the printed external terminal at the center of the protective film thereof.