JPH03280468A - Semiconductor device and its manufacturing method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device and a method for manufacturing the same, and in particular,
The present invention relates to a semiconductor device formed on an insulating amorphous material and a method for manufacturing the same.

[Prior art] Insulating amorphous substrates such as glass and quartz, SiO2, 5i
Attempts have been made to form high performance semiconductor devices on insulating amorphous materials such as insulating amorphous layers such as 3Nn.

In recent years, as the need for large, high-resolution liquid crystal display panels, high-speed, high-resolution contact image sensors, three-dimensional ICs, etc. has increased, semiconductor elements formed on insulating amorphous materials such as those mentioned above are becoming more and more popular. High performance is expected.

Taking the case of forming a thin film transistor (TFT) on an insulating amorphous material as an example, (1) TPT whose element material is amorphous silicon formed by plasma CVD method, etc.
2) TPT whose element material is polycrystalline silicon formed by a CVD method, etc., (3) TPT whose element material is made of single crystal silicon formed by a melt recrystallization method, etc. are being considered.

However, among these TPTs, TPTs made of amorphous silicon or polycrystalline silicon have significantly lower field-effect mobilities than those made of single-crystal silicon (amorphous silicon TFT < 1c
m2/V-see, polycrystalline silicon TFT
~10 cm'/V-5ec), it was difficult to realize a high-performance TPT.

On the other hand, the melting and recrystallization method using laser beams, etc. is still not a fully developed technology, and is particularly difficult when it is necessary to form elements over a large area, such as in liquid crystal display panels. big.

[Problem to be solved by the invention] Therefore, a method of solid-phase growth of large-grain polycrystalline silicon has attracted attention as a simple and practical method for forming high-performance semiconductor elements on insulating amorphous materials. and research is underway. (Thin 5 solid films)
Vol, 100 No. 3 (1983) p, 227
, JJAP Vol. 25 No. 2 (1986)
p, LL21) Normally, undoped polycrystalline silicon is used for the channel region, and n-type poly-3i doped with impurities at high temperature is used for the gate electrode. N-type poly-3i has the advantage that a low-resistance gate electrode can be formed relatively easily by a diffusion method of heating in PCIo3 gas.

On the other hand, in order to improve the performance of TPT, a method is generally known in which the TPT is hydrogenated using H2 plasma or the like to reduce the trap level at the crystal grain boundary of the channel. In this case, if the gate electrode is made of n-type pO1y-3i, the hydrogenated non-doped poly-3i exhibits properties closer to n-type, so the threshold voltage (vth) of the TFT will vary from -1V to 1V in the case of an n-channel TPT. There was a problem that there was a shift of about -5v, and a shift of about -0.5v to -1.5v in the p channel. In particular, the shift amount of vth tends to be larger for a poly-3i TFT formed by a solid-phase epitaxy method or the like and hydrogenated by a hydrogen plasma treatment or the like and has better characteristics. In order to control vth, conventionally, a method has been used in which the channel poly-3i of TPT is doped with a small amount of boron, a so-called channel doping method, to make poly-3i closer to the p-type. When poly-3i TFTs are formed by low pressure CVD, etc., by optimizing the dose, vth can be adjusted to minimize the off-state current of both p-channel TPT and n-channel TPT with one channel ion implantation. In some cases, it is possible to control this, and conventional methods have been effective in this case. poly-
When a 3iTFT is formed by a low pressure CVD method, etc., the gate voltage at which the drain current is minimum (more precisely, it is the gate voltage at which the drain current starts to rapidly increase almost exponentially, hereinafter referred to as Vmin) is 11 in n channel
V for the p channel, and about -0.5 v for the p channel, and it was possible to control vth so that Vmin was approximately Ov for both the n channel and the p channel by one channel ion implantation. On the other hand, poly-8i T
In TPT with excellent characteristics, in which the FT is formed by solid-phase growth, etc. and hydrogenated by hydrogen plasma treatment, etc., the amount of shift in vth tends to be large, and the difference in the amount of shift between n-channel and p-channel tends to increase. In this case, it is difficult to control vth so that Vmin becomes Ov for both the n-channel and p-channel in one channel ion implantation, and it is difficult to control vth so that the n-channel and p-channel are set to the optimal dose I separately. , it was necessary to implant the channel ion implant. Therefore, there was a problem that the number of steps was increased by one step, making it more complicated.The present invention is intended to solve the above problems, and its purpose is to provide TPT having good characteristics with a simpler manufacturing process. There is a particular thing.

[Means to solve the problem] The semiconductor device of the present invention has the following features.

(1) In a semiconductor device in which at least a part of the channel region of an insulated gate field effect transistor is made of a non-single crystal semiconductor, the gate electrode is made of a p-type semiconductor and at least a part of the channel region of an n-channel transistor is made of a non-single crystal semiconductor. It is characterized in that it contains a p-type impurity such as boron, but does not contain the impurity in the channel region of the p-channel transistor.

(2) The non-single crystal semiconductor is made of polycrystalline silicon.

(3) The polycrystalline silicon includes crystal grains having a grain size of 1 μm or more.

(4) The p-type semiconductor forming the gate electrode has a crystal grain size of 1
It is characterized by being made of polycrystalline silicon containing crystal grains of μm or more.

Furthermore, the method for manufacturing a semiconductor device of the present invention has the following features.

(1) In a method for manufacturing a semiconductor device in which at least a part of a channel region of an insulated gate field effect transistor is made of a non-single crystal semiconductor, and a p-channel transistor and an n-channel transistor are formed on the same substrate, the n-channel transistor The method is characterized in that it includes at least the step of introducing p-type impurities into at least the channel region, and the step of forming the gate electrode from a p-type semiconductor.

(2) The non-single crystal semiconductor is made of polycrystalline silicon.

(3) The polycrystalline silicon includes crystal grains having a grain size of 1 μm or more.

(4) The polycrystalline silicon is formed by a solid phase growth method.

(5) The p-type semiconductor forming the gate electrode has a crystal grain size of 1
It is characterized by being made of polycrystalline silicon containing crystal grains of μm or larger.

[Example] Hereinafter, the present invention will be described in detail based on FIG. 1. FIG. 1 is a manufacturing process diagram of a semiconductor device based on the present invention.

FIG. 1(a) shows an insulating amorphous substrate such as glass or quartz;
Or an insulating amorphous material layer such as 5iCh or 5izN4, or a sapphire substrate (A120z) or Mg
A non-monocrystalline silicon layer 102 such as microcrystalline silicon or polycrystalline silicon is formed by 100 to 200 layers on an insulating material 101 such as an insulating crystal substrate such as O.Al2O3, BP, or CaF2.
The non-single crystal silicon layer is etched into a predetermined pattern, and the SiO2 layer forming the gate insulating film 103 is etched at about 300 Å or more by thermal oxidation or sputtering.
This is the process of forming approximately 1,500 people.

As a method for forming the non-single crystal silicon layer, there are the following methods.

(1) Deposit a polycrystalline silicon thin film at about 580° C. to 650° C. by low pressure CVD method.

(2) After depositing an amorphous silicon thin film using EB (Electron Beam) evaporation, sputtering, plasma CVD, etc., open-phase growth annealing (laser annealing) at approximately 550°C to 650°C for approximately 2 to 70 hours is performed. There is also a method to polycrystallize in a short time using
A polycrystalline silicon thin film having a large grain size as described above is formed.

(3) After depositing a polycrystalline silicon thin film by low pressure CVD method etc.
After implanting Si or the like using the ion implantation method to make the polycrystalline silicon thin film amorphous, solid-phase growth annealing is performed at approximately 550°C to 650°C (there is also a method to polycrystallize it in a short time using laser annealing method, etc.) ) to obtain a grain size of 1 to 2 μm.
A thin film of polycrystalline silicon with a large grain size is formed.

In addition, when polycrystalline silicon is formed by the above method, there are cases where the crystallinity is close to 100%, literally polycrystalline silicon, and cases where the crystallinity is about 50% to 90%. There are cases.

In this case, it may be more appropriate to call the latter microcrystalline silicon rather than polycrystalline silicon, but in this patent, unless otherwise specified, both will be referred to as polycrystalline silicon. . Further, as the non-monocrystalline silicon thin film, microcrystalline silicon or amorphous silicon thin film may be used in addition to the above-mentioned polycrystalline silicon thin film.

An example of film forming conditions will be described below. Using the plasma CVD method, the substrate temperature is maintained at room temperature to about 600°C, monosilane or a gas made by diluting monosilane with hydrogen, argon, helium, etc. is introduced into the reaction chamber, and high frequency energy etc. are applied to decompose the gas and form the desired substrate. Silicon layer on top with a thickness of 10
Approximately 0A to 2,000 people will be formed. Subsequently, the silicon layer is crystal-grown by heat treatment or the like to form a polycrystalline silicon layer.

The optimum conditions for the heat treatment vary depending on the method of forming the silicon layer. For example, there are differences as described below depending on the substrate temperature during film formation.

(1) Films formed using the plasma CVD method at a relatively low temperature between room temperature and 150°C become amorphous silicon containing a large amount of hydrogen, but films formed at temperatures between 200 and 300°C become amorphous silicon. Hydrogen in the film can be removed by heat treatment at a lower temperature than in the case of a thin film. An example of heat treatment conditions will be described below. After film formation by plasma CVD, the amorphous silicon film is annealed before breaking the vacuum. Amorphous silicon films, which are formed at low deposition temperatures, are porous films, so if they are taken out into the atmosphere after being deposited, oxygen, etc. are likely to be incorporated into the film, causing a decline in film quality. When an appropriate heat treatment is performed on the film, the film is densified and the incorporation of oxygen and the like is prevented.

The heat treatment temperature is preferably 300°C or higher, and 400 to 500°C.
The effect is particularly great when the temperature is raised to about .degree. C., and even if the heat treatment temperature is less than 300.degree. C., the effect of densification of the film by heat treatment remains. However, if annealing is performed continuously without breaking the vacuum, this annealing can be omitted.

Subsequently, the amorphous silicon film is grown in a solid phase by heat treatment or the like. When an amorphous silicon film formed at a low deposition temperature is subjected to heat treatment at a relatively low temperature of about 550°C to 650°C for several hours to 20 hours, hydrogen desorption and crystal growth occur, resulting in a crystal grain size of 1. Polycrystalline silicon containing large crystal grains of about 2 μm or more is formed. Incidentally, in both the annealing for densification and the annealing during solid phase growth, it is not preferable to raise the temperature rapidly in a short period of time when raising the temperature to a predetermined annealing temperature.The reason is that as the temperature is raised, (Especially when the temperature exceeds 300° C.) hydrogen in the film is desorbed, and if the temperature rise rate is rapid, defects are likely to be formed in the film. In some cases, pinholes may form,
The film may peel off. At temperatures above 300° C., defects in the film will be reduced if the temperature is gradually increased at a heating rate slower than 20° C./min (a heating rate slower than 5° C./min is particularly preferred).

(2) The substrate temperature is 150℃~300℃ using plasma CVD method.
In a film formed at a temperature of about .degree. C., the amount of hydrogen in the film is reduced compared to the amorphous silicon film formed at a low temperature, but the temperature at which hydrogen is desorbed is shifted to a higher temperature side. However, since the film after formation is denser than a film formed at a low temperature, the above-described annealing for densification can be omitted. The solid-phase growth conditions are heat treatment at about 550°C to 650°C for several hours to about 40 hours, which causes hydrogen desorption and crystal growth, including large crystal grains with a crystal grain size of about 1 to 2 μm. Polycrystalline silicon is formed. In addition, the method of raising the temperature from 550℃ to 650℃ is at least 30℃ as in the case of (1).
20"07 minutes at temperatures above 0°C (preferably 5°C/
It is preferable to gradually increase the temperature at a rate slower than 150 min) to reduce defects in the film.
Between 'C and 200'C, the crystal grain size is relatively large;
It is particularly preferable because peeling of the film, which occurs when the temperature is raised to a predetermined solid phase growth temperature during solid phase growth, is less likely to occur.

(3) When the substrate temperature exceeds 300°C, the amount of hydrogen in the film further decreases, but when annealing at about 550°C to 650°C, hydrogen desorption occurs and the film becomes thin. Heat treatment may be important.

FIG. 1(b) is a step in which channel ion implantation is selectively performed only on the n-channel TPT.

In the figure, 104 indicates a pattern of resist, etc. formed on the p-channel TFT. As an example of ion implantation conditions, when the thickness of the polycrystalline silicon layer forming the channel region is about 350A to 550A, the accelerating voltage Dosage of boron at about 30 to 70 keV 5 x 1
By driving in about 0” to 5 x 10”cm-2,
vth can be controlled so that Vmin is approximately Ov. The boron hide in the channel part is 1015~10"cm-
The optimum value is within the range of 10Ia~10"cm
-' level is particularly desirable.

FIG. 1(C) shows an a-3i layer doped with boron on the 5i02 layer by means such as plasma CVD, ECR-PCVD, sputtering, and Si ion implantation into a polycrystalline Si thin film. 105 to about 3000
In this embodiment, a plasma CVD method is used as an example to explain the process of forming 0 to 7000A. SiH4 and H2 gases were used as film-forming gases in the plasma CVD method, and B2H6 gas was used as a doping gas. Substrate temperature is 150-250
℃, internal pressure is 0.8 Torr, 13.56 MHz rf
Power supply was used. The flow rate ratio of B2H6 and SiH4 is [B
2H6] / [3i H4] ~3 X 10-'~
It was set to be about 5×10-'. Note that the temperature of boron contained in the formed a-3i layer approximately corresponds to the above-mentioned gas mixture ratio.

FIG. 1(d) shows a step in which the a-3i layer 105 is grown in a solid phase and patterned into the shape of a gate electrode 106.

Note that solid phase growth may be performed after pattern formation.

The substrate in this state is pre-annealed at 450° C. for 30 ml in a N2 atmosphere to eliminate hydrogen contained in the a-8i layer. The purpose of this is to prevent the formation of vacancies in the portions from which hydrogen has escaped, resulting in a porous film, if solid phase growth annealing is performed while hydrogen is still contained in a-8i. still,
When using the plasma CVD method, it is more desirable to dilute the film-forming gas with He gas because it has the advantage of reducing the amount of hydrogen taken into the a-3i layer. Move on to the annealing process.

The annealing conditions are about 4 to 72 hours at a temperature of 550 to 650° C. in N2 gas. By this solid-phase growth annealing, the a-8i layer becomes polycrystalline, and the average grain size of the Si grains in the gate electrode becomes about 1 to 3 μm, and many grains appear without reducing the grain size to 5 μm or more. The annealing is not limited to N2 annealing, and may be laser beam annealing, halogen lamp annealing, etc. During this annealing process, the boron atoms mixed during the a-3i layer formation are simultaneously activated. As a result, the polycrystalline silicon gate electrode (
The resistivity of p+poly-3i)106 is 1-3×10
The resistivity of an n-type doped gate electrode using polycrystalline Si with an average grain size of 3000 Å or less and containing no crystal grains of 1 μm or more formed by ordinary LPGVD is 2.5xlO-'Ω. cm and approximately the same resistivity can be obtained.

FIG. 1(e) shows a step of implanting P ions in the case of an n-channel TPT and B ions in the case of a p-channel TPT using the gate electrode as a mask to form a source region 108 and a drain region 107. After this, for the purpose of activating the source and drain regions,
This activation annealing, in which N2 annealing is performed at approximately 1000°C, simultaneously achieves complete activation of the BIM element in the gate electrode 105 and an increase in the crystallization rate, and the resistivity of the gate electrode becomes lXl0-'Ω・Cm. It goes down below. It is also suitable to form the gate electrode a-3i by ECR-PCVD. The a-3i layer formed by ECR-PCVD has the advantage that the hydrogen content in the film can be reduced, so that briannealing for dehydrogenation can be omitted. Or Journal of Non-Crys
talline 5olids vol, 10? p,
295 (1989), an a-Si layer may be formed using a remote plasma CVD method at a substrate temperature of 370°C or higher. According to this method, the a-Si layer contained in the a-5i layer Since hydrogen can be reduced to almost completely zero, it is more suitable for solid phase growth.

FIG. 1(f) shows the CVD method, Braz? This is a step of forming a Si02 layer 109 forming an interlayer insulating film by a CVD method, a sputtering method, or the like. The insulating film between the eyebrows may be a silicon nitride film, etc. At this stage, hydrogen is introduced into the active layer by a method such as hydrogen plasma method, hydrogen ion implantation method, or hydrogen diffusion method from a nitride film formed by plasma CVD method. As a result, dangling bonds existing at the gate insulating film/Si interface, crystal grain boundaries, etc. are terminated, and the density of defect levels is reduced.

Such a hydrogenation step may be performed before laminating the interlayer insulating film.

In Fig. 1(g), contact holes for the source and drain are opened and a conductive film (Al, Or, ITO, etc.) of the wiring material is removed.
In this step, a film is formed to a thickness of approximately 1 μm to 1 μm using a sputtering method to form a source electrode 111 and a drain electrode 110.

Incidentally, the present invention is based on the first ri! It is not limited to the example of J, but polycrystalline silicon is used as a layer material on an insulating material,
It is widely effective in forming insulated gate field effect transistors.

Next, Fig. 2 shows the gate voltage-drain current characteristic diagram of the p-channel TPT, and Fig. 3 shows the gate voltage-drain current characteristic diagram of the n-channel TPT. In both figures, amorphous silicon formed by the plasma CVD method was grown by the solid phase growth method. Poly-8i TFT with polycrystalline structure and gate insulating film formed using thermal oxidation method
FIG.

In FIG. 2, 201 shows TFT characteristics based on the present invention, and 202 shows conventional TPT characteristics using n-type poly-3i for the gate electrode and without channel ion implantation.The voltage between the source and drain is -5V. or,
In FIG. 3, 301 shows <TPT characteristics based on the present invention, and 302 shows conventional TPT characteristics using n-type poly-3i for the gate electrode and without channel ion implantation.The voltage between the source and drain is It is 5v. p channel T P T.

In order to control vth so that Vmin becomes Ov for both n-channel TPT, it was necessary to perform channel ion implantation for the p-channel TPT and n-channel TPT separately, but according to the present invention, channel ion implantation can be performed in one time. With only channel ion implantation, vth is adjusted so that Vmin is approximately Ov for both p-channel TPT and n-channel TFT.
can be controlled. The mechanism by which Vth can be controlled for both the p-channel TPT and the n-channel TPT according to the present invention will be described below. p-type poly-8
When i is used for the gate electrode, the gate voltage that achieves a flat band state in the gate electrode/insulating film/semiconductor structure is about lv higher than in the case of an n-type poly-8i gate. In p-channel TPT, n-type poly-3
When using an i gate electrode, TPT'Vmin is -I
The gate electrode can be changed from n-type to p-type without performing channel ion implantation (Fig. 2, 202).
By changing the type, Vth can be controlled so that Vm-in becomes approximately Ov (FIG. 2, 201).
On the other hand, when using an n-type poly-3i gate electrode with an n-channel TPT, the Vmin of the TPT is between -5V and -6V.
(Fig. 3, 302), and unlike p-channel TPT, it is not possible to make Vmin OV just by using a p-type poly-8i gate electrode.
By using a p-type poly-3i gate electrode and performing appropriate channel ion implantation, Vmin can be reduced to approximately O.
Vth can be controlled so that it becomes v (FIG. 3, 301).

In this way, using a p-type poly-8i gate electrode,
By selectively implanting channel ions only in channel TPT, vth is adjusted so that Vmin becomes Ov for both channels.
can be controlled. Therefore, compared to the conventional method that required channel ion implantation to be performed twice for each p-channel and n-channel, the number of steps is smaller, and p
Good TPT characteristics can be obtained for both channel and n-channel. Furthermore, the present invention provides poly-
Not only when poly-3i is formed by a solid phase growth method or laser annealing method, but also when formed by a conventionally commonly used method such as forming poly-3i by LPCVD method, p-channel TPT, n Both vth of the channel TPT can be strictly controlled, which has the effect of reducing current consumption.

According to the above-described manufacturing method, reduction in gate wiring resistance and control of vth, which were difficult to achieve with n-type polycrystalline silicon formed by conventional LPCVD and thermal diffusion methods, can be easily achieved through extremely simple steps. Therefore, it is possible to reduce gate wiring resistance, which has conventionally been a problem in active TPT large-sized liquid crystal panels, and the liquid crystal panel can be easily applied to HDTVs and the like.

Furthermore, when the present invention is applied to a contact image sensor in which a scanning circuit and a photoelectric conversion element are integrated on the same substrate, it has a significant effect on faster reading speed, higher resolution, and higher gradation. . Furthermore, the effect of reducing the gate wiring allows the contact type image sensor to be made longer, which has a great effect on increasing the size of the image sensor. Similarly, applications to TPT-driven liquid crystal shutter arrays, TPT-driven thermal heads, etc. are also possible. In addition to the application to TPT, 3
Application to dimensional ICs, etc. is also possible.

[Effects of the Invention] According to the semiconductor device and the manufacturing method thereof of the present invention, the manufacturing process is simpler and poly-
3i TFT vth control can be realized 6 The present invention is a TP with excellent characteristics in which the channel portion is formed by solid phase growth method etc.
It is particularly effective against T. Further, according to the present invention,
Since the resistivity of the gate electrode can be lowered, it has a great effect on devices where it is essential to lower the gate wiring resistance, such as active matrix TPT large liquid crystal panels. Therefore, it becomes easy to apply TPT liquid crystal panels to HDTVs and the like.

Furthermore, when the present invention is applied to a contact image sensor in which a scanning circuit and a charge conversion element are integrated on the same substrate, it has a significant effect on faster reading speed, higher resolution, and higher gradation. . Furthermore, the effect of reducing the gate wiring allows the contact type image sensor to be made longer, which has a great effect on increasing the size of the image sensor. Similarly, applications to TPT-driven liquid crystal shutter arrays, TPT-driven thermal heads, etc. are also possible. In addition to the application to TPT, 3
Application to dimensional ICs, etc. is also possible.

[Brief explanation of drawings]

FIG. 1 is a manufacturing process diagram of a semiconductor device of the present invention. FIG. 2 is a gate voltage-drain current characteristic diagram of the present invention and a conventional p-channel TPT. FIG. 3 is a gate voltage-drain current characteristic diagram of the present invention and a conventional n-channel TPT. 01...Insulating material 02...Non-single crystal silicon layer 03...Gate insulating film 05...Boron-doped a-9i layer 06...
... Gate electrode 07 ... Drain region 08 ... Source region 09 ... Interlayer insulating film 10 ... Drain electrode ... Source electrode or higher

Claims (9)

[Claims] (1) In a semiconductor device in which at least a part of the channel region of an insulated gate field effect transistor is made of a non-single crystal semiconductor, the gate electrode is made of a p-type semiconductor and at least a part of the channel region of an n-channel transistor is made of a non-single crystal semiconductor. 1. A semiconductor device that contains a p-type impurity such as boron, but does not contain the impurity in a channel region of a p-channel transistor. (2) The semiconductor device according to claim 1, wherein the non-single crystal semiconductor is made of polycrystalline silicon. (3) The semiconductor device according to claim 2, wherein the polycrystalline silicon includes crystal grains having a crystal grain size of 1 μm or more. (4) The p-type semiconductor forming the gate electrode has a crystal grain size of 1
4. The semiconductor device according to claim 1, wherein the semiconductor device is made of polycrystalline silicon containing crystal grains of μm or more. (5) In a method for manufacturing a semiconductor device in which at least a part of a channel region of an insulated gate field effect transistor is made of a non-single crystal semiconductor, and a p-channel transistor and an n-channel transistor are formed on the same substrate, the n-channel transistor 1. A method of manufacturing a semiconductor device, comprising at least the steps of introducing p-type impurities into at least a channel region of the semiconductor device, and forming a gate electrode from a p-type semiconductor. (6) The method of manufacturing a semiconductor device according to claim 5, wherein the non-single crystal semiconductor is made of polycrystalline silicon. (7) The method for manufacturing a semiconductor device according to claim 6, wherein the polycrystalline silicon includes crystal grains having a crystal grain size of 1 μm or more. (8) The method of manufacturing a semiconductor device according to claim 7, wherein the polycrystalline silicon is formed by a solid phase growth method. (9) The p-type semiconductor forming the gate electrode has a crystal grain size of 1
9. The method of manufacturing a semiconductor device according to claim 5, 6, 7, or 8, characterized in that the semiconductor device is made of polycrystalline silicon containing crystal grains of μm or more.