JPH03280537A - Epitaxial growth substrate - Google Patents
Epitaxial growth substrateInfo
- Publication number
- JPH03280537A JPH03280537A JP8204790A JP8204790A JPH03280537A JP H03280537 A JPH03280537 A JP H03280537A JP 8204790 A JP8204790 A JP 8204790A JP 8204790 A JP8204790 A JP 8204790A JP H03280537 A JPH03280537 A JP H03280537A
- Authority
- JP
- Japan
- Prior art keywords
- epitaxial growth
- substrate
- mirror
- crown
- main surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 29
- 230000003746 surface roughness Effects 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 abstract description 10
- 239000010703 silicon Substances 0.000 abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 9
- 239000004065 semiconductor Substances 0.000 abstract description 8
- 230000015572 biosynthetic process Effects 0.000 abstract description 6
- 238000000206 photolithography Methods 0.000 description 5
- 238000005498 polishing Methods 0.000 description 5
- 235000012431 wafers Nutrition 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 239000004744 fabric Substances 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
Landscapes
- Mechanical Treatment Of Semiconductor (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、クラウンの発生を効果的に防止することので
きるエピタキシャル成長用基板及びエピタキシャルウェ
ーハの製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an epitaxial growth substrate and an epitaxial wafer manufacturing method that can effectively prevent the occurrence of crowns.
従来、半導体装置の製造において、トランジスタの直列
抵抗の低減や素子分離を行うために、基板上にエピタキ
シャル成長がよくおこなわれる。Conventionally, in the manufacture of semiconductor devices, epitaxial growth is often performed on a substrate in order to reduce the series resistance of transistors and to isolate elements.
このとき、シリコン単結晶基板周端部において、エピタ
キシャル成長時に異常成長が起こり、成長層の主表面よ
りも高くなる現象がある。この主表面より高くなる突起
はクラウンと呼ばれている。At this time, there is a phenomenon in which abnormal growth occurs at the peripheral edge of the silicon single crystal substrate during epitaxial growth, resulting in the growth layer being higher than the main surface. This protrusion that is higher than the main surface is called a crown.
このクラウンは、主表面よりも高いために、半導体装置
製造工程のホトリソグラフィ工程に悪影響を及ぼし、パ
ターン形成が著しく不完全なものとなるという欠点があ
った。Since this crown is higher than the main surface, it has a disadvantage in that it adversely affects the photolithography process of the semiconductor device manufacturing process, resulting in extremely incomplete pattern formation.
クラウン発生防止のため、従来がら面取りが行′われで
おり、主表面に対する面取り斜面部の角度を１６度以下
として、クラウンの発生を解消する従業もなされている
（特開昭５９−２２７１１７号公報）、シかし、主表面
に対する面取り斜面部の角度が大きい場合には、依然と
してクラウンの発生を有効に防止する手段は知られてい
ない。In order to prevent the formation of crowns, chamfering has traditionally been performed, and some efforts have been made to eliminate the formation of crowns by setting the angle of the chamfered slope to the main surface to 16 degrees or less (Japanese Patent Laid-Open No. 59-227117). ) However, when the angle of the chamfered slope with respect to the main surface is large, there is still no known means for effectively preventing the formation of crowns.
なお、エピタキシャル成長用基板の面取り斜面部の鏡面
加工は従来行われた例はなかった。Incidentally, mirror finishing of the chamfered slope portion of the substrate for epitaxial growth has not been previously performed.
本発明は、上記した従来技術の問題点を解消するために
発明されたもので、エピタキシャル成長を行う際に生成
するクラウンの発生を防止し、ホトリソグラフィ工程に
おいて基板に圧接するマスクがクラウンによる損傷をう
けることがなく、基板に対するマスクの密接が良好に達
成されてホトリソグラフィの精度が向上し、半導体素子
、半導体装置の品質、信顛性等が向上するようにしたエ
ピタキシャル成長用基板及びエピタキシャルウェーハの
製造方法を提供することを目的とする。The present invention was invented to solve the above-mentioned problems of the prior art, and it prevents the occurrence of crowns that occur during epitaxial growth, and prevents damage caused by the crowns to the mask that is pressed against the substrate in the photolithography process. Manufacturing of substrates for epitaxial growth and epitaxial wafers that are free from damage, achieve good close contact of a mask to the substrate, improve the accuracy of photolithography, and improve the quality, reliability, etc. of semiconductor elements and semiconductor devices. The purpose is to provide a method.
上記課題を解決するために、本発明のエピタキシャル成
長用基板においては、この基板の面取り斜面部に鏡面加
工を施すものである。In order to solve the above problems, in the epitaxial growth substrate of the present invention, the chamfered slope portion of the substrate is mirror-finished.
また、本発明のエピタキシャルウェーハの製造方法にお
いては、基板の主表面の鏡面加工と併せて面取り斜面部
の鏡面加工を行い、エピタキシャル成長におけるクラウ
ンの発生を防止したものである。Further, in the method for manufacturing an epitaxial wafer of the present invention, the main surface of the substrate is mirror-finished and the chamfered slope portion is mirror-finished to prevent the occurrence of a crown during epitaxial growth.
上記鏡面加工した面取り斜面部の最大面粗さ（Ｒｍａｘ
）を１１１ｍ以下とすることが好ましい、この面取り
斜面部の最大面粗さ（Ｒｍａｘ ）は、面取り斜面部の
鏡面加工度を向上するほど小さくなり、鏡面加工度を上
げる程、即ち最大面粗さ（ＲｓａＸ）を小さくすればす
るほどクラウンの発生が抑制される。The maximum surface roughness of the mirror-finished chamfered slope part (Rmax
) is preferably 111 m or less. The maximum surface roughness (Rmax) of this chamfered slope becomes smaller as the degree of mirror finishing of the chamfered slope increases, and as the degree of mirror finishing increases, the maximum surface roughness The smaller (RsaX) is, the more the occurrence of crown is suppressed.
このクラウン発生の抑制の理由は、面取り部の面粗さを
小さくすることによって、面取り部表面の微小凹凸の山
谷の高度差が小さくなり、このためかかる表面にエピタ
キシャル成長が起きると、山に析出した半導体原子がよ
り容易に谷を埋めることが可能になり、その結果全体と
してクラウンの発生が防止されるものと考えられる。従
って、面取り部の而粗さが小さければ、面取り部の斜面
部の主表面との傾斜が大きくなってもクラウンは発生し
ない。The reason for this suppression of crown formation is that by reducing the surface roughness of the chamfer, the height difference between the peaks and troughs of the minute irregularities on the surface of the chamfer becomes smaller, and therefore, when epitaxial growth occurs on such a surface, precipitation occurs in the peaks. It is believed that the semiconductor atoms can more easily fill the valleys, and as a result, the generation of crowns is prevented as a whole. Therefore, if the roughness of the chamfered portion is small, crowning will not occur even if the slope of the chamfered portion with respect to the main surface becomes large.
以下に実施例を挙げて本発明をさらに具体的に説明する
。The present invention will be explained in more detail with reference to Examples below.
第１図は、シリコン基板２の断面図である。同図におい
て、４は主表面であり、６は面取り斜面部である。該基
板２の主表面４と面取り斜面部６とのなす角が面取り角
度θである。FIG. 1 is a cross-sectional view of the silicon substrate 2. FIG. In the figure, 4 is the main surface, and 6 is a chamfered slope. The angle formed by the main surface 4 of the substrate 2 and the chamfered slope portion 6 is the chamfer angle θ.
第２図は、該シリコン基板２にエピタキシャル成長を行
って厚さ１０μｍのエピタキシャル層８を形成した場合
のシリコン基板２の断面図である、同図で示すように、
面取り開始部分Ｐに突起部、即ちクラウンＣが形成され
る。FIG. 2 is a cross-sectional view of the silicon substrate 2 when an epitaxial layer 8 with a thickness of 10 μm is formed on the silicon substrate 2 by epitaxial growth.
A protrusion, ie, a crown C, is formed at the chamfering start portion P.
本発明の特徴は、面取り斜面部６に鏡面加工を施すこと
である。即ち、鏡面加工を施した面取り斜面部６を形成
することによって、面取り開始部分Ｐに形成される突起
部、即ちクラウンＣの発生を抑えることが可能となるも
のである。A feature of the present invention is that the chamfered slope portion 6 is mirror-finished. That is, by forming the mirror-finished chamfered slope portion 6, it is possible to suppress the occurrence of a protrusion, that is, a crown C, formed at the chamfering start portion P.
面取り斜面部６の鏡面加工の程度とエピタキシャル成長
におけるクラウンの発生との相関についての具体的な実
験結果について以下に述べる。Specific experimental results regarding the correlation between the degree of mirror finishing of the chamfered slope portion 6 and the occurrence of a crown during epitaxial growth will be described below.
シリコン基板（６″φ、厚さ５６５μｍ、面取り角度０
８２２度）を用い、面取り条件〔■鏡面加工なし、最大
面粗さ（Ｒｇ＋＋ａｘ ） −２〜３μｍ、■研磨布に
よる鏡面研磨１５秒、最大面粗さ（Ｒｓｅａχ）＝１〜
２μｍ、■研磨布による鏡面研磨２４０秒〕、エビクキ
シャル条件（バレル形エピタキシャル成長炉、成長温度
１１３０℃、シリコンソースニトリクロロシラン、エピ
タキシャル層厚さ：ｌＯμｍ）を設定し、各１０枚の基
板についてエピタキシャル成長を行った。得られたエピ
タキシャルウェーハについて、各ウェーハの４カ所につ
いてクラウン高さを測定して、その結果を第１表に示し
た。なお、面取り斜面部の最大面粗さ（Ｒｓａｘ ）の
測定には、面粗さ計（接触式面粗さ計、メーカー：ベル
テン社、Ｆ型式：Ｓ６Ｐ、仕様針：先ｉ６０° ２
μｍＲ）を使用した。Silicon substrate (6″φ, thickness 565μm, chamfer angle 0
822 degrees), chamfering conditions [■ No mirror polishing, maximum surface roughness (Rg++ax) -2 to 3 μm, ■ Mirror polishing with polishing cloth for 15 seconds, maximum surface roughness (Rseaχ) = 1 to
2 μm, mirror polishing with polishing cloth for 240 seconds] and epitaxial conditions (barrel-type epitaxial growth furnace, growth temperature 1130°C, silicon source nitrichlorosilane, epitaxial layer thickness: 10 μm) were set, and epitaxial growth was performed on each of 10 substrates. Ta. The crown heights of the obtained epitaxial wafers were measured at four locations on each wafer, and the results are shown in Table 1. In addition, to measure the maximum surface roughness (Rsax) of the chamfered slope part, a surface roughness meter (contact type surface roughness meter, manufacturer: Belten, F model: S6P, specification needle: tip i60° 2
μmR) was used.
第１表
第１表から、面取り部６の表面の最大面粗さ（Ｒｓ＋ａ
χ）を１μｍ以下とすれば、面取り開始部分Ｐに形成さ
れる突起部、即ちクラウンＣの発生を抑えることが可能
であることがわかった。さらに、最大面粗さ（Ｒｓａｘ
）を小さくすればするほどクラウンＣの発生が抑制され
ることが示されている。換言すれば、鏡面加工度を向上
するほどクラウンＣの発生が抑えられることとなる。Table 1 From Table 1, the maximum surface roughness of the surface of the chamfered portion 6 (Rs+a
It has been found that by setting χ) to 1 μm or less, it is possible to suppress the occurrence of a protrusion, that is, a crown C, formed at the chamfering start portion P. Furthermore, the maximum surface roughness (Rsax
) is shown to suppress the occurrence of crown C. In other words, the more the degree of mirror finishing is improved, the more the occurrence of crown C can be suppressed.
以上述べたごとく、本発明によれば、エピタキシャル成
長を行う際に生成するクラウンの発生を防止し、ホトリ
ソグラフィ工程において基板に圧接するマスクがクラウ
ンによる損傷をうけることがなく、基板に対するマスク
の密接が良好に達成されてホトリソグラフィの精度が向
上し、半導体素子、半導体装置の品質、信頼性等が向上
するという効果が達成される。As described above, according to the present invention, it is possible to prevent the formation of a crown that is generated during epitaxial growth, and the mask that is in pressure contact with the substrate in the photolithography process is not damaged by the crown, and the close contact between the mask and the substrate is prevented. This is successfully achieved, and the effects of improving the accuracy of photolithography and improving the quality, reliability, etc. of semiconductor elements and semiconductor devices are achieved.
第１図は本発明のシリコン基板の断面図及び第２図はシ
リコン基板にエピタキシャル成長を行ったときの断面図
である。
２・・−シリコン基板、４−・・主表面、６−面取り部
、８−エピタキシャル層、Ｃ−・クラウン、Ｐ・・・面
取り開始部分。FIG. 1 is a sectional view of a silicon substrate of the present invention, and FIG. 2 is a sectional view of the silicon substrate after epitaxial growth. 2--silicon substrate, 4--main surface, 6--chamfered portion, 8--epitaxial layer, C--crown, P--chamfering start portion.
Claims (4)
工を施してなるエピタキシャル成長用基板において、面
取り斜面部に鏡面加工を施したことを特徴とするエピタ
キシャル成長用基板。(1) An epitaxial growth substrate having a main surface and a chamfered slope portion, the main surface of which is mirror-finished, characterized in that the chamfered slope portion is mirror-finished.
ｍａｘ）を１μｍ以下としたことを特徴とする請求項（
１）記載のエピタキシャル成長用基板。(2) Maximum surface roughness (R
max) is 1 μm or less (
1) The substrate for epitaxial growth described above.
ル成長を行うエピタキシャルウェーハの製造方法におい
て、基板の面取り斜面部に鏡面加工を併せて行いエピタ
キシャル成長におけるクラウンの発生を防止するように
したことを特徴とするエピタキシャルウェーハの製造方
法。(3) A method for manufacturing an epitaxial wafer in which the main surface of the substrate is mirror-finished and then epitaxial growth is performed, in which mirror-finishing is also performed on the chamfered slope portion of the substrate to prevent the occurrence of crowns during epitaxial growth. A method for manufacturing an epitaxial wafer.
ｍａｘ）を１μｍ以下としたことを特徴とする請求項（
３）記載のエピタキシャルウェーハの製造方法。(4) Maximum surface roughness (R
max) is 1 μm or less (
3) The method for manufacturing the epitaxial wafer described above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2082047A JP2594371B2 (en) | 1990-03-29 | 1990-03-29 | Manufacturing method of epitaxial wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2082047A JP2594371B2 (en) | 1990-03-29 | 1990-03-29 | Manufacturing method of epitaxial wafer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03280537A true JPH03280537A (en) | 1991-12-11 |
| JP2594371B2 JP2594371B2 (en) | 1997-03-26 |
Family
ID=13763602
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2082047A Expired - Lifetime JP2594371B2 (en) | 1990-03-29 | 1990-03-29 | Manufacturing method of epitaxial wafer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2594371B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7195545B2 (en) | 2003-04-02 | 2007-03-27 | Sumitomo Electric Industries, Ltd. | Chamfered freestanding nitride semiconductor wafer and method of chamfering nitride semiconductor wafer |
| JP2011091143A (en) * | 2009-10-21 | 2011-05-06 | Sumco Corp | Method of manufacturing silicon epitaxial wafer |
| WO2012066761A1 (en) * | 2010-11-15 | 2012-05-24 | Sumco Corporation | Method of producing epitaxial wafer and the epitaxial wafer |
| JP2017204504A (en) * | 2016-05-09 | 2017-11-16 | 信越半導体株式会社 | Epitaxial wafer evaluation method |
| JP2022098256A (en) * | 2020-12-21 | 2022-07-01 | Ｊｘ金属株式会社 | Indium phosphide substrate, method for manufacturing the same, and semiconductor epitaxial wafer |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5865429A (en) * | 1981-07-06 | 1983-04-19 | イ−ストマン・コダツク・カンパニ− | Color developing pigment precursor compound and corresponding phenazine pigment |
| JPS59107520A (en) * | 1982-12-13 | 1984-06-21 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor substrate |
-
1990
- 1990-03-29 JP JP2082047A patent/JP2594371B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5865429A (en) * | 1981-07-06 | 1983-04-19 | イ−ストマン・コダツク・カンパニ− | Color developing pigment precursor compound and corresponding phenazine pigment |
| JPS59107520A (en) * | 1982-12-13 | 1984-06-21 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor substrate |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7195545B2 (en) | 2003-04-02 | 2007-03-27 | Sumitomo Electric Industries, Ltd. | Chamfered freestanding nitride semiconductor wafer and method of chamfering nitride semiconductor wafer |
| KR100713039B1 (en) * | 2003-04-02 | 2007-05-02 | 스미토모덴키고교가부시키가이샤 | Method of processing edges of nitride semiconductor substrate |
| US7550780B2 (en) | 2003-04-02 | 2009-06-23 | Sumitomo Electric Industries, Ltd. | Chamfered freestanding nitride semiconductor wafer and method of chamfering nitride semiconductor wafer |
| US8022438B2 (en) | 2003-04-02 | 2011-09-20 | Sumitomo Electric Industries, Ltd. | Chamfered freestanding nitride semiconductor wafer and method of chamfering nitride semiconductor wafer |
| US8482032B2 (en) | 2003-04-02 | 2013-07-09 | Sumitomo Electric Industries, Ltd. | Chamfered freestanding nitride semiconductor wafer and method of chamfering nitride semiconductor wafer |
| JP2011091143A (en) * | 2009-10-21 | 2011-05-06 | Sumco Corp | Method of manufacturing silicon epitaxial wafer |
| WO2012066761A1 (en) * | 2010-11-15 | 2012-05-24 | Sumco Corporation | Method of producing epitaxial wafer and the epitaxial wafer |
| JP2012109310A (en) * | 2010-11-15 | 2012-06-07 | Sumco Corp | Method for manufacturing epitaxial wafer, and epitaxial wafer |
| JP2017204504A (en) * | 2016-05-09 | 2017-11-16 | 信越半導体株式会社 | Epitaxial wafer evaluation method |
| JP2022098256A (en) * | 2020-12-21 | 2022-07-01 | Ｊｘ金属株式会社 | Indium phosphide substrate, method for manufacturing the same, and semiconductor epitaxial wafer |
| EP4207249A4 (en) * | 2020-12-21 | 2024-11-20 | JX Nippon Mining & Metals Corporation | Indium phosphide substrate, method for manufacturing indium phosphide substrate, and semiconductor epitaxial wafer |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2594371B2 (en) | 1997-03-26 |
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