JPH03280622A - Analog/digital converter - Google Patents

Abstract

PURPOSE:To attain A/D conversion with accuracy over bit accuracy of an A/D converter in use by presetting an initial digital value corresponding to a level of a synchronizing signal to a storage circuit when the synchronizing signal appears in an input analog signal and applying A/D conversion to a level of a difference signal for each clock period succeedingly and adding the result. CONSTITUTION:When a synchronizing signal appears in an input analog signal, an initial digital value corresponding to a level of the synchronizing signal is preset to a storage circuit 18, and a level of a difference signal for each clock period obtained from a differential amplifier circuit 13 is converted into a digital value at an A/D converter circuit 16. Then the value is added to the initial digital value by an adder circuit 17, the sum is stored into the storage circuit 18, from which the value subject to A/D conversion is outputted. Thus, the A/D converter circuit 16 does not need to convert the analog signal of the maximum amplitude into a digital value and is enough to be a circuit applying A/D conversion to a level of a difference signal for each clock period. Thus, a digital signal in a bit number over a bit number of the A/D converter circuit in use is outputted and the accuracy is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application This invention is for converting analog signals, such as camera CCD output signals and video signals, which have periodicity and include synchronization signals with a fixed level into digital signals. The present invention relates to an analog/digital conversion device.

Conventional technology Analog/digital (A/D) conversion circuit.

It converts an input analog signal into a digital signal with the number of bits corresponding to the bit precision of the A/D conversion circuit. For example, an 8-bit A/D conversion circuit performs A/D conversion with a maximum accuracy of 8 bits.

Problems to be Solved by the Invention In conventional A/D conversion circuits, the precision with which it can be converted into a digital signal depends on its bit precision.
A/D conversion could not be performed with a precision higher than the bit precision of the /D conversion circuit. For example, it has not been possible to obtain a digital value of 10171 or more using a 6-bit or 8-bit A/D conversion circuit.

Means for Solving the Problems The present invention provides a device for converting an input analog signal into a digital signal, which has a periodicity and includes a synchronization signal with a fixed level at a predetermined position. A sample-and-hold circuit that samples and holds the level of the input analog signal; an analog delay circuit that inputs the analog signal level held by the sample-and-hold circuit and outputs the delayed clock cycle; A differential circuit outputs an analog signal at a level representing the difference between the held analog signal level and the delayed analog signal level delayed by the analog delay circuit, and the difference level represented by the output analog signal of the differential circuit is determined by the clock period. Analog/
The digital (A/D) conversion circuit presets an initial digital value corresponding to the level of the synchronizing signal at the time of output of the synchronizing signal in the input analog signal, and updates the digital value representing the addition result inputted every clock cycle. The digital value outputted from the A/D conversion circuit at each clock cycle is added to the initial digital value stored in the storage circuit or the digital value representing the addition result, and the addition result is The present invention is characterized in that it includes an adder circuit that stores the represented digital value in the storage circuit. The digital value representing the addition result stored in the storage circuit becomes the final digital output signal of this analog/digital converter.

When a synchronization signal appears in the active input analog signal, an initial digital value corresponding to the level of the synchronization signal is preset in the storage circuit. After this, the level of the difference signal for each clock cycle obtained from the differential circuit is converted into a digital value by the A/D conversion circuit, and added to the initial digital value by the addition circuit (in the case of a negative value, the level is substantially is subtracted) and stored in the storage circuit. The digital value (added value for each clock cycle) stored in the storage circuit or the A/D converted value will be output. When the synchronization signal appears again, the above operation is repeated.

Embodiments Hereinafter, embodiments in which the present invention is applied to A/D conversion of video signals will be described in detail.

FIG. 1 is a block diagram showing an example of an A/D conversion device. Figure 2 shows the video signal, clock pulse and 0PC
3 is a time chart showing an L (optical clasp) pulse. The video signal includes an IH initial horizontal synchronization signal. The level of the horizontal synchronization signal is set to H level, and the levels on both sides thereof are set to be 5sync death level. The clock pulse defines the A/D conversion period, and every clock pulse period T
One cycle of operation of the circuit of FIG. 1, including conversion, is performed. This clock pulse is omitted from illustration in FIG. The 0PCL pulse is a timing pulse that represents the timing at which the horizontal synchronization signal appears.

First, the principle of A/D conversion will be briefly explained. In the initial value setting circuit 22, an initial value (digital value) Do corresponding to the pedestal level of the video signal is set in advance, and when the pedestal level appears (preferably) in response to the input of the 0PCL pulse. is the initial value (at the end of the pedestal level). is preset in the memory circuit 18. The differential amplifier circuit 13 outputs a difference signal of the video signal every cycle T of the clock pulse, and this difference signal is converted into a digital value D by the A/D conversion circuit I6. Digital value D representing this difference
is added to the value stored in the storage circuit 18 by the addition circuit 17, and the result of this addition is stored in the storage circuit 18, thereby updating the storage contents. Therefore, the initial value Do
When the time nT has elapsed since the preset, the memory contents of the memory circuit 18 are filled.

+ΣD. This value is the input video signal,
It is output as a digital conversion value of n. When the period of 1H has passed, the initial value is stored in the memory circuit 18 again. or preset.

In this way, the A/D conversion circuit 16 only needs to have an A/D conversion range capable of A/D conversion of the difference signal, and moreover,
It is possible to digitally convert an input analog signal having an amplitude greater than the A/D conversion range of the D conversion circuit. Furthermore, since the initial value Do is preset in the storage circuit 18 for each IH, accumulation of errors is prevented and highly accurate A/D conversion is possible.

Next, this embodiment will be described in detail.

Analog video input signal is sample and hold circuit 1
1 is given. The sample-and-hold circuit 11 samples and holds the input analog signal at the period T of the clock pulse, and applies the sampled values to the positive input terminal of the differential amplifier circuit 13 and the delay circuit I2, respectively. The delay circuit 12 delays the input signal by one clock period T and outputs the delayed signal. This output is given to the negative input terminal of the differential amplifier circuit 13.

The difference between these two human input signals is calculated by the differential amplifier circuit 13, and is applied to the automatic gain adjustment circuit 14 for amplification.

The automatic gain adjustment circuit 14 performs A/D conversion using this A/D converter.
This is to ensure that the output digital value after D conversion falls within a predetermined range, and its gain is adjusted by the control device 20. The control device 20 monitors the A/D-converted digital signal outputted from the storage circuit 18 at the timing of the 0PCL pulse, and determines the difference between the digital value representing the video signal H and the digital value representing the Bedestar sync level. The gain of the automatic gain adjustment circuit 14 is controlled so that it is always constant.

The difference signal amplified by the automatic gain adjustment circuit 14 is given to a clamp circuit 15. The clamp circuit 15 is.

The clamp level is controlled by the controller 20 via the clamp level control circuit 21 in response to the 0PCL Hals. That is, when the pedestal level is input to the clamp circuit 15 (the pedestal level is constant, the difference signal is 0 at this time), the level of the output signal of the clamp circuit 15 is set to the next stage A/D. The clamp level is controlled to correspond to the center of the dynamic range of the conversion circuit 16. Specifically, the clamp level is controlled so that when the output of the automatic gain adjustment circuit 14 is O, the output of the clamp circuit 15 is zero.

The output signal of the clamp circuit 15 is then sent to the A/D conversion circuit 16.
and as its output one clock pulse period T
A digital value D representing the difference between the two is obtained.

The output digital value D of the A/D conversion circuit 16 is added to the value stored in the storage circuit 18 in the addition circuit 17 as described above, and the result of the addition is stored in the storage circuit 18. The stored digital value of the storage circuit 18 is applied to a limiter 19, so that it is limited to within a certain value, and is output as a final digital value.

Effects of the Invention According to this invention, when a synchronization signal appears in the input analog signal as described above, an initial digital value corresponding to the level of the synchronization signal is preset in the storage circuit, and from then on, the digital value obtained from the differential circuit is preset. The level of the difference signal for each clock cycle is converted into a digital value by an A/D conversion circuit,
The adder circuit adds the value to the initial digital value (in the case of a negative value, it is essentially subtracted) and stores it in the storage circuit. The digital value (added value for each clock cycle) stored in the storage circuit is output as an A/D converted value. When the synchronization signal appears again, the above operation is repeated.

The A/D conversion circuit A/D converts the level of the difference signal for each clock cycle. In other words, the A/D conversion circuit does not need to convert the analog value of the maximum amplitude (the difference between the maximum level and the minimum level) of the input analog signal into a digital value, but converts the level of the difference signal for each clock cycle into a digital value. Therefore, the A/D conversion range may be narrow.

In other words, it is possible to output a digital signal with a bit number greater than the bit number of the A/D conversion circuit used, and the accuracy can be improved. Furthermore, since the memory circuit is preset for each synchronization signal included in the input analog signal, it is possible to prevent errors from accumulating over one cycle or more of the input analog signal, thereby providing highly accurate output.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the invention. Figure 2 shows analog signals, clock pulses and 0PC
It is a time chart showing an L pulse. 11...Sample/hold circuit. 12...Delay circuit. 13...Differential amplifier circuit. 16...A/D conversion circuit. 17...Addition circuit. 18...Memory circuit. that's all

Claims (3)

[Claims] (1) In a device that converts an input analog signal that has periodicity and includes a synchronization signal with a fixed level at a predetermined position into a digital signal, the level of the input analog signal is changed at a clock cycle representing the analog/digital conversion cycle. A sample-and-hold circuit that samples and holds the sample; an analog delay circuit that inputs the analog signal level held by the sample-and-hold circuit, delays the clock cycle, and outputs the analog signal level held by the sample-and-hold circuit; and a delayed analog signal level delayed by the analog delay circuit, a differential circuit that outputs an analog signal at a level representing the difference between the signal level and the delayed analog signal level delayed by the analog delay circuit, and converts the difference level represented by the output analog signal of the differential circuit into a digital value every clock cycle. An analog/digital conversion circuit that presets an initial digital value corresponding to the level of the synchronizing signal at the time of output of the synchronizing signal in the input analog signal, and stores the digital value representing the addition result that is input every clock cycle while updating. memory circuit,
The digital value output from the analog/digital conversion circuit is added to the initial digital value or the digital value representing the addition result stored in the storage circuit every clock cycle, and the digital value representing the addition result is stored in the storage circuit. An analog/digital conversion device comprising: an adder circuit that is stored in the storage circuit, and outputs a digital value representing the addition result stored in the storage circuit. (2) Claim (1) further comprising a variable gain amplifier circuit that amplifies the output signal of the differential circuit with an amplification factor controlled so that the digital value output from the storage circuit falls within a predetermined range. The analog/digital conversion device described in . (3) When a synchronization signal appears in the input analog signal and this synchronization signal is maintained at a constant level for at least two clock cycles, the level of the output analog signal of the differential circuit or variable gain amplifier circuit is at a predetermined level. The analog/digital conversion device according to claim 1, further comprising a clamp circuit that clamps the output signal of the differential circuit or the variable gain amplifier circuit so that the output signal of the differential circuit or the variable gain amplifier circuit becomes .