JPH0328062B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a - group compound semiconductor device, and particularly to a compound semiconductor field effect transistor in which the carrier concentration on the source side and the drain side in the channel region is changed by the piezoelectric polarization effect. Microelectronics has become the foundation of modern industrial progress and has had a major impact on social life. Silicon (Si) semiconductor devices are currently the mainstay of microelectronics, and the miniaturization of transistor elements has had a great effect on speeding up and increasing the degree of integration. Furthermore, in order to achieve improvements in operating speed that exceed the limits based on the physical properties of silicon, semiconductor devices using compound semiconductors such as gallium arsenide (GaAs), whose carrier mobility is much higher than that of silicon, have been developed. As a transistor using a compound semiconductor,
Although the development of field effect transistors, especially shot-barrier field effect transistors, has been advanced due to their simple manufacturing process, efforts have been made to commercialize integrated circuit devices that take full advantage of their advantages. It is being [Prior art] Schottky barrier field effect transistors (hereinafter abbreviated as MESFETs) are currently made of compound semiconductors,
In particular, there are many examples in which GaAs is used as the semiconductor material, and an example of its structure is shown in the schematic side sectional view of FIG. In the conventional example shown in the figure, an n-type channel layer 12 is formed on a semi-insulating GaAs substrate 11, for example, by ion implantation or by a GaAs epitaxial growth layer doped with impurities.
A gate electrode 13 is disposed on the shaped channel layer 12 and in contact therewith. Impurities are introduced by an ion implantation method using this gate electrode 13 as a mask to form n ⁺ source and drain regions 14 with a higher impurity concentration than the n-type channel layer 12, and an insulating film 15 is deposited.
Source and drain electrodes 16 are provided in ohmic contact with the n ⁺ type source and drain regions 14. In the conventional example, in order to increase the speed, GaAs is used as the material of the substrate 11 as mentioned earlier, and its electron mobility μ is increased from about 1500 cm ³ /Vsec of Si to 400 cm ³ /Vsec.
It has been increased to a certain extent. Also, regarding the structure, in order to achieve higher speed and higher integration.
Progress is being made in miniaturizing MES FET elements and shortening the gate length. However, as the gate length is shortened, the range of variation from the expected values in characteristics such as gate threshold voltage Vth and K value gradually increases, and this variation depends on the direction of the gate with respect to the zone axis of the GaAs semiconductor substrate. It's different. As causes of this so-called short channel effect, attention has been focused on the penetration of highly concentrated impurities introduced into the source and drain regions 14 into the channel layer 12 and the piezoelectric polarization effect mainly caused in the compound semiconductor substrate by the insulating film 15. . Piezoelectric polarization is, for example, due to the stress exerted on the semiconductor substrate by the gate electrode 13, insulating film 15, etc. of a GaAsMES FET, the Ga and As atoms constituting the substrate crystal are displaced, resulting in a polarization charge distribution as shown in FIG. 2. The variation in the gate threshold voltage is due to the change in the distribution of carriers in the channel layer 12 due to polarized charges, and the expansion and contraction of the shot depletion layer. (e.g. PMAsbeck et al.; IEEE Transa−
ctionson Electron Devices, Vol.ED−31, No.
(Refer to 100ct.1984) This means that in compound semiconductors such as - group,
This occurs because the crystal is asymmetric. Furthermore, in order to increase the speed of semiconductor devices, it is naturally effective to increase the electric field strength E in order to increase the carrier drift velocity v = μE (μ is the carrier mobility, E is the electric field strength). The source-drain voltage etc. in conventional examples are limited by power consumption, withstand voltage, etc., and all conventionally known means of locally forming an electric field are complicated, and the electric field effect of miniaturized and highly integrated It is not suitable for implementation in transistor devices. [Problems to be Solved by the Invention] As explained above, the speed of semiconductor devices is increasing, but in order to fully meet expectations for compound semiconductor devices, highly integrated field effect transistor elements that are miniaturized are required. What is needed is a means to locally create an electric field that increases the drift velocity of the carrier in the channel region of the channel. [Means for solving the problem] The above problem is solved by using a (110)-plane - group compound semiconductor, forming a gate electrode so that the drain current flows in the [001] axis direction, and using this compound semiconductor substrate. This problem is solved by the present invention, which utilizes the fact that when an insulating film is coated on the gate electrode, the polarity of the piezoelectric polarization is different on both sides of the gate electrode, or in other words, the carrier concentration in the channel is different on the source side and the drain side. In order to make the drain electrode flow in the [001] axis direction, the gate width direction of the gate electrode should be adjusted to [11].
0] direction. [Function] The present inventors have investigated the piezoelectric polarization effect based on the stress generated in the − group compound semiconductor substrate, the material and thickness of the insulating film, the crystal plane of the semiconductor substrate, the crystal zone axis, and the state of piezoelectric polarization due to this stress. By studying the correlation, we found that when the gate width direction of the (110) plane of a GaAs single crystal is in the [110] direction, the polarity of piezoelectric polarization is different on both sides of the gate electrode, that is, on the source side and the drain side.We obtained the following results. ing.

【table】

〔Example〕

The present invention will be specifically explained below using examples. FIG. 4 is a schematic side sectional view showing an embodiment of the present invention related to a GaAsMES FET. In this example, (110) of the semi-insulating GaAs substrate 1 is
For example, if Si is applied to the surface at an energy of 59 keV, the dose
Ions are implanted to a concentration of about 0.9×10 ¹² cm ^-2 and activated by heat treatment to achieve an impurity concentration of about 5 to 6×10 ¹⁶ cm ^-3 .
A shaped channel layer 2 is provided. On this GaAs substrate 1 surface, a gate electrode 3 is formed, for example, using tungsten silicide (WsSi ₃ ) or the like, with the gate width direction in the [110] direction and the gate length about 1 μm. For example, on the substrate 1 using the gate electrode 3 as a mask,
Si at energy 175keV, dose 1.7×10 ¹³ cm
Ions are implanted to about ^-2 and activation heat treatment is performed to form n ⁺ type source and drain regions 4S and 4D with an impurity concentration of about 1×10 ¹⁸ cm ^-3 . For example, plasma chemical vapor deposition (P-CVD)
A SiO ₂ film 5 is coated on a semi-insulating GaAs substrate to a thickness of, for example, about 1200 nm using a method (method). After this, the SiO ₂ film 5 is opened to form a source/drain electrode. On the n ⁺ type source and drain regions 4S and 4D,
For example, the source electrode 6 and the drain electrode 7 are formed using gold germanium/gold (AuGe/Au). The distance between the source electrode 6 or drain electrode 7 and the gate electrode 3 is, for example, about 2 μm. In this embodiment, positive charges appear on the source side of the channel region and negative charges appear on the drain side due to the piezoelectric polarization, and an electric field (fifth
The carrier electrons are accelerated by qVbi in the figure. Figures 6a and 6b show the MES FET created according to the present invention.
and the conventional method (without using piezoelectric polarization charge)
This is the result of comparing the K value (corresponds to g _n ; the larger the better) and the γ value (corresponds to the drain conductance; the smaller the better) of the MES FET. From this result, it is obvious that the present invention is effective in improving the characteristics of field effect transistors. As described above, the drift speed of the carrier electrons increases, the operating speed increases, and effects such as an increase in the transfer conductance gm and an improvement in the drain conductance can be obtained. Although the above description is directed to GaAsMES FETs, the present invention also applies to field effect transistors using other − group compound semiconductor materials, or using junction type, MIS type, and heterojunctions (e.g., HEMT). A similar effect can be obtained by the method. [Effects of the Invention] As explained above, according to the present invention, the drift speed of the carrier in the channel of the - group compound semiconductor field effect transistor is increased, and effects such as increased speed, increased gm, and improved drain conductance can be obtained. It will be done. This improves the characteristics of the field effect transistor and has a great effect on the practical application of compound semiconductor integrated circuit devices. Note that the present invention can be broadly applied to any field effect transistor. Therefore, it is applicable to shot gate type FET, HEMT, MIS, and junction type FET.

[Brief explanation of the drawing]

Fig. 1 is a cross-sectional view of a conventional general field effect transistor, Fig. 2 is a cross-sectional view showing an example of distribution of piezoelectric polarization charges in a conventional field effect transistor, and Fig. 3 is a cross-sectional view of a conventional field effect transistor. Cross-sectional view showing an example of distribution of piezoelectric polarization charges of a field effect transistor, No. 4
The figure is a cross-sectional view of the structure of a field effect transistor according to the present invention, FIG. 5 is an energy band diagram, and FIG.
b is a graph showing a comparison of K value and γ value of field effect transistors of the present invention and a conventional example; In the figure, 13, 3... gate, 15, 5... insulating film, 6... source electrode, 7... drain electrode.

Claims (1)

[Claims] 1. The crystal plane orientation of the surface is the (110) plane.
a group compound semiconductor layer; a source electrode and a drain electrode provided on the compound semiconductor layer and arranged so that a drain current flows in the [001] axis direction; and the compound semiconductor between the source electrode and the drain electrode. A semiconductor device comprising: a gate electrode formed on a layer; and an insulating film provided on the compound semiconductor layer.