JPH0328060B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, particularly to modification of a semiconductor integrated circuit device in which a plurality of field effect transistor elements are formed on a - group compound semiconductor wafer.

Microelectronics has become the foundation of modern industrial progress and has had a major impact on social life. Silicon (Si) semiconductor devices are currently the mainstay of microelectronics, and the miniaturization of transistor elements has had a great effect on speeding up and increasing the degree of integration.

Furthermore, in order to achieve improvements in operating speed that exceed the limits based on the physical properties of silicon, semiconductor devices using compound semiconductors such as gallium arsenide (GaAs), whose carrier mobility is much higher than that of silicon, have been developed.

As a transistor using a compound semiconductor,
Although field effect transistors, especially shot-barrier field effect transistors, have been developed earlier due to their simple manufacturing process, efforts have been made to commercialize integrated circuit devices that take full advantage of their characteristics. It is being

[Conventional technology]

Schottky barrier field effect transistors (hereinafter abbreviated as MES FETs) are currently made of compound semiconductors.
In particular, there are many examples in which GaAs is used as the semiconductor material, and an example of its structure is shown in the schematic side sectional view of FIG.

In the conventional example shown in the figure, an n-type channel layer 2 is formed on the (100) plane of a semi-insulating GaAs substrate 1 by, for example, ion implantation, and a gate electrode is in contact with the n-type channel layer 2. 3 is arranged.

Impurities are introduced into the n-type channel layer 2 by an ion implantation method using the gate electrode 3 as a mask.
N ⁺ -type source and drain regions 4 with higher impurity concentration are formed, an insulating film 5 is deposited, and source and drain electrodes 6 are provided in ohmic contact with the n ⁺ -type source and drain regions 4 .

Integrated circuit devices are constructed using MES FETs as described above, and in order to increase their speed and integration,
As the miniaturization of MES FET elements progresses and their gate lengths are shortened, the range of variation in characteristics such as gate threshold voltage Vth from the expected value gradually increases, and Therefore, the direction of variation of this gate threshold voltage Vth differs.

Figure 2 shows an MES in which the gate width direction is in the [011] direction of the crystal zone axis, which is perpendicular to the GaAs (100) single crystal plane.
An example of gate threshold voltage Vth variation between FET and MES FET in the [011] direction is shown, and the gate length is 2 μm.
Below this level, there is a tendency for the [011] direction to fluctuate in the positive direction, while in the [011] direction it fluctuates significantly in the negative direction.

Therefore, in an integrated circuit device in which MES FET elements are arranged in two directions in this way, if the gate length deviates from the design value due to variations during the manufacturing process, for example, the amount of variation in the gate threshold voltage Vth will be relatively large. Conventionally, the gate direction is usually limited to one direction because the desired circuit operation cannot be obtained.

FIG. 3 shows an example in which the X and Y address decoder circuits of a storage device are constructed using MES FET elements whose gate widths are in the same direction.

As shown in FIG. 3A, the output line 14 of the X decoder 11 and the output line 15 of the Y decoder 12 are connected to the memory cell matrix 13 in a perpendicular direction. As for the X decoder 11, its output line 14 and
By aligning the width direction of the gate electrode G of the MES FET element with, for example, the [011] direction, it is possible to form an efficient pattern.

On the other hand, in the Y decoder 12, the MES FET
When the width direction of the gate electrode G of the element is aligned in the same [011] direction as the X decoder 11, this becomes a direction perpendicular to the output line 15. For this purpose, the gate electrode G is branched into a comb shape, and a large number of sources S and drains D are arranged to obtain a gate width equivalent to that of the X decoder 11, as shown in FIG. This pattern is shown in Figure b
The pattern is more complex than that of the previous one, making miniaturization and high integration difficult in both the design and manufacturing process.

As the causes of the so-called short channel effect mentioned above, attention is focused on the penetration of high concentration impurities introduced into the source and drain regions 4 into the channel layer 2 and the effect of piezoelectric polarization generated in the semiconductor substrate mainly by the insulating film 5. has been done.

Changes in characteristics due to this piezoelectric polarization are caused by MES FET
an insulating film 5 provided in contact with the semiconductor substrate of the element;
The stress exerted on the semiconductor substrate by the gate electrode 3 causes piezoelectric polarization in the compound semiconductor substrate, and the chiral distribution in the channel layer 2 changes and the shot depletion layer expands and contracts, so that the gate threshold voltage Vth increases.
varies, and the direction of the variation is either positive or negative depending on the polarity of the piezoelectric polarization determined by the stress direction and the crystal zone axis direction.

(e.g. PMAsbeck et al.; IEEE
Transactions on Electron Devices, Vol.ED
(Refer to -31, No. 10, Oct. 1984 pp. 1377-1380) This seems to occur because, especially in the case of - group compound semiconductors, their crystallinity is asymmetric because they are compounds.

[Problem that the invention seeks to solve]

As explained above, in the conventional structure, variations in the characteristics of the compound semiconductor field effect transistor become extremely large as the gate length is shortened, and in particular, orthogonal arrangement is extremely difficult.

In order to overcome this current situation, there is a strong demand for a semiconductor device whose characteristics are stable even when miniaturized FET elements are arranged in different directions, such as perpendicular to each other, and which allows for an increase in the degree of integration.

[Means for solving problems]

The above problem is that the principal plane is the (110) plane.
A plurality of gate electrodes are formed on the main surface of the group compound semiconductor substrate, an insulating film is formed on the plurality of gate electrodes and the main surface, and a plurality of gate electrodes are formed on the compound semiconductor substrate and the plurality of gate electrodes. A semiconductor device according to the invention is characterized in that a field effect transistor element is formed and the plurality of gate electrodes have different gate directions.

[Effect]

The present inventors have studied, for example, the stress generated in a − group compound semiconductor substrate such as GaAs, the material and thickness of an insulating film, the crystal plane of the semiconductor substrate, the crystal zone axis and the state of piezoelectric polarization caused by this stress, the gate threshold of a field effect transistor. We study the correlation between voltage and K value and the state of piezoelectric polarization, and for example, when the insulating film is silicon dioxide (SiO ₂ ), we investigate the relationship between the crystal plane of a GaAs single crystal substrate, the gate axis direction of an n-channel MESFET, etc. The following results were obtained regarding the relationship between the gate threshold voltage Vth and the direction of variation.

First, when the gate width direction is set to [110] and [110] directions on the GaAs (100) plane as shown in Fig. 4a,
Figure b shows the dependence of the gate threshold voltage on the gate length for various SiO ₂ film thicknesses when the gates are formed on the GaAs (110) plane with the gate width directed in the [001] and [110] directions.

As a result, the direction of Vth variation is opposite in the [011] direction and the [011] direction, which are perpendicular to each other on the (100) plane, as described above, whereas the [001] direction which is orthogonal to each other on the (100) plane ] direction and [110] direction are Vth
The fluctuation direction of Vth is the same direction, the value of Vth itself is also a very close value, and the dependence on the SiO ₂ film thickness is also extremely small.

More specifically, when a gate electrode with the gate width direction in the [110] direction is formed, for example, from tungsten silicide (WSi) on the (110) plane of a GaAs semiconductor substrate, and a SiO ₂ film is deposited, the piezoelectric polarization charge is The distribution is shown in Figure 5. In the same figure, A is 1×10 ¹⁶
cm ^-3 or more, B is 5 × 10 ¹⁵ cm ^-3 or more, C is 1 × 10 ¹⁵
cm ^-3 or higher, D represents a concentration of 5 x 10 ¹⁴ cm ^-3 or higher, - represents a negative charge, and no sign represents a positive charge.

As is clear from the figure, the sign of the piezoelectric polarization charge is reversed on the left and right sides with the center of the gate electrode as the border.
The absolute values are equal. For this reason,
The positive and negative influences on the depletion layer of the FET channel act to cancel each other out. Therefore, the variation in Vth of the [110] FET due to the piezoelectric effect is small. Furthermore, since the sign of the piezoelectric polarization charge is reversed on the left and right sides of the FET, it has the effect of accelerating the movement of carriers within the channel. For this reason, a normal FET
The transconductance gm is larger than that of the current, and if used for the purpose of driving current in an integrated circuit, it can be used to improve the operating speed.

Further, in the FET in the [001] direction perpendicular to this, no piezoelectric polarization charge is induced at all. For this reason, the fourth
As shown in Figure b, the Vth of [001] FET is
There is no dependence on SiO ₂ film thickness.

Furthermore, on the (110) plane, for any direction,
Fluctuations in FET characteristics due to piezoelectric effects are extremely small.
Controlling the gate threshold voltage Vth is very easy.Due to the characteristics of this (110) plane, there is no difference in piezoelectric polarization effect between FETs formed on this plane whose gate directions are perpendicular to each other, and the channel length is Even if the length is shortened, there will be no difference in characteristics such as gate threshold voltage between FETs with different directions. Also, the gate direction is oblique.
Differences in characteristics between FETs are minimal. This provides ease of integrated circuit design.

〔Example〕

The present invention will be specifically explained below using examples.

FIG. 6 is a schematic plan view showing the process order of an embodiment of the present invention relating to an integrated circuit device having an E/D configuration using GaAs MES FET as a basic element.

In this example, a semi-insulating film with (110) plane as the main surface is used.
An inverter consisting of an E (enhancement) mode (hereinafter referred to as subscript E) and a D (depletion) mode (hereinafter referred to as subscript D) MES FET elements is mounted on a GaAs substrate, with the gate width direction of each [001] Direction (hereinafter represented by subscript 1) and [110]
direction (hereinafter represented by subscript 2).

Refer to FIG. 6a. For example, silicon (Si) is ion-implanted into the (110) plane of the semi-insulating GaAs substrate 21 as described below to form the n-type channel region 2 of each element.

D mode channel regions 22 _D1 and 22 _D2 , energy 59kev, dose 1.7×10 ¹² cm ^-2 E mode channel regions 22 _E1 and 22 _E2 , energy 59kev, dose 0.9×10 ¹² cm ^-2 After ion implantation, A protective film (not shown) such as aluminum nitride (AIN) is provided on one surface of the substrate,
For example, activation heat treatment is performed at a temperature of 850° C. for about 15 minutes.

Refer to FIG. 6b. For example, W ₅ Si ₃ is deposited to a thickness of about 400 mm by sputtering or the like on the surface of the substrate 1, and this is patterned to form each gate electrode 23. In this embodiment, the gate length is approximately 1 μm.

Refer to FIG. 6c. Using the gate electrode 23 as a mask, for example,
Si at energy 175kev, dose 1.7×10 ¹³ cm
Ion implantation is performed at a temperature of about ^-2 , for example at a temperature of 750°C for a period of time.
Activation heat treatment is performed for about 10 minutes to form n ⁺ type source and drain regions 24.

See Figure 6d. For example, plasma chemical vapor deposition method (P-
A silicon nitride (SiNx) film (not shown) is deposited to a thickness of, for example, about 500 mm over the entire surface of the substrate 1 including the gate electrode by CVD (CVD method).

Openings are formed in SiNx above the n ⁺ type source and drain regions 24, and gold/germanium/gold/germanium/
The source and drain electrodes 25 and the like are formed to a thickness of about 250 mm using gold (AuGe/Au) or the like.

In this example, two types of gates with orthogonal gate directions are used.
In the MES FET element, the difference in gate threshold voltage Vth for each of the D and E modes is only a few tens of mV at a gate length of 1 μm, and it is possible to use them completely equally.

Regarding the conventional decoder described above, both X and Y decoders can be obtained using MES FET elements having the same pattern, and it is possible to form an arbitrary integrated circuit.

Further, although the above description is directed to GaAs MES FETs, similar effects can be obtained by the method of the present invention using other compound semiconductor materials, or with junction type or MIS type field effect transistors.

〔Effect of the invention〕

As explained above, according to the present invention, even if the gate directions of compound semiconductor field effect transistors are arranged in arbitrary mutually orthogonal directions and the channel length is shortened, characteristics such as gate threshold voltage can be made uniform. This makes it possible to reduce the difference in characteristics even in the case of diagonal crossing, resulting in a great effect on the practical application of compound semiconductor integrated circuit devices.

[Brief explanation of drawings]

FIG. 1 is a schematic side sectional view showing a conventional example of MES FET, FIG. 2 is a diagram showing a conventional example of MES FET characteristics, and FIG. 3a is a schematic plan view showing an example of a decoder.
Figures 3b and 3c are schematic plan views showing conventional examples of MES FET elements in decoders, Figure 4a is a diagram showing conventional examples of MES FET characteristics, and Figure 4b is a diagram showing the characteristics of MES FETs according to the present invention. A diagram showing the effect, Figure 5 is GaAs
A piezoelectric polarization charge distribution diagram when a SiO ₂ film is deposited on the (110) plane with a gate width in the [110] direction. Figures 6a to 6d are schematic plan views in the order of steps showing embodiments of the present invention. It is. In the figure, 21 is a semi-insulating GaAs substrate, 22
is an n-type channel region, 23 is a gate electrode, and 24 is an n-type channel region.
n ⁺ type source and drain regions, 25 is source and drain electrode, subscript D is depletion mode,
Subscript E is enhancement mode, subscript 1 is gate width direction [001], subscript 2 is gate width direction [11]
0].

Claims (1)

[Claims] 1. A plurality of gate electrodes are formed on the main surface of a - group compound semiconductor substrate whose main surface is a (110) plane, and an insulating film is formed on the plurality of gate electrodes and on the main surface. A semiconductor integrated circuit device, wherein a plurality of field effect transistor elements are formed by the compound semiconductor substrate and the plurality of gate electrodes, and the plurality of gate electrodes have different gate directions. 2. The semiconductor device according to claim 1, wherein the different gate directions are directions perpendicular to each other.