JPH03280739A - Reception timing phase setting system in digital signal transmission and reception circuit - Google Patents
Reception timing phase setting system in digital signal transmission and reception circuitInfo
- Publication number
- JPH03280739A JPH03280739A JP2082612A JP8261290A JPH03280739A JP H03280739 A JPH03280739 A JP H03280739A JP 2082612 A JP2082612 A JP 2082612A JP 8261290 A JP8261290 A JP 8261290A JP H03280739 A JPH03280739 A JP H03280739A
- Authority
- JP
- Japan
- Prior art keywords
- timing
- phase
- circuit
- reception
- transmitting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000008054 signal transmission Effects 0.000 title description 2
- 230000005540 biological transmission Effects 0.000 claims abstract description 39
- 238000012549 training Methods 0.000 claims abstract description 11
- 238000012360 testing method Methods 0.000 claims abstract description 8
- 230000003111 delayed effect Effects 0.000 claims abstract description 6
- 230000007175 bidirectional communication Effects 0.000 claims description 3
- 238000000034 method Methods 0.000 claims description 3
- 230000006854 communication Effects 0.000 abstract description 7
- 238000004891 communication Methods 0.000 abstract description 7
- 238000010586 diagram Methods 0.000 description 6
- 241000772415 Neovison vison Species 0.000 description 2
- 230000001934 delay Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000002457 bidirectional effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
Landscapes
- Dc Digital Transmission (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はディジタル信号送受信回路における受信タイミ
ング位相設定方式に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a reception timing phase setting method in a digital signal transmission/reception circuit.
従来、2つの送受信回路間で双方向のディジタル通信を
行うときには、伝送路遅延の変動を吸収するために、送
信波形を送り出す送信タイミングと受信信号を打抜いて
受信シンボルを復元する受信タイミングとは独立とする
ことが多い。Conventionally, when performing bidirectional digital communication between two transmitter/receiver circuits, in order to absorb fluctuations in transmission path delay, there is a transmission timing at which the transmission waveform is sent out, and a reception timing at which the reception signal is punched out to restore the reception symbols. Often independent.
また、通信する2つの送受信回路を従属同期で動かす場
合には、一方をマスタ、他方をスレーブとし、マスタ側
の送信タイミングがら決まるマスター・スレーブ方向の
信号の最適位相をスレーブ側の受信タイミングが打抜く
ように従属同期さぜ、スI−・−グ側の送信タイミング
はスレ・−ブ側の受信タイミングど同一とし、マスタ側
の受信タイミングはスl、−ブーマスタ方向の信号の最
適位相を打抜くように従属同期、′5ぜるのが一般的で
ある。In addition, when operating two communicating transmitter/receiver circuits in slave synchronization, one is set as the master and the other is the slave, and the reception timing on the slave side matches the optimal phase of the signal in the master-slave direction, which is determined by the transmission timing on the master side. For slave synchronization, the transmission timing on the slave side is the same as the reception timing on the slave side, and the reception timing on the master side is set to match the optimum phase of the signal in the master direction. It is common to remove slave synchronization, '5.
、二のようなタイミング位相の調整は通計1トレニング
」ど呼ばれる通f3の前段階において行われる。, 2, etc., are performed in the stage before the step f3, which is called ``total 1 training''.
第3図は通常のディジクル通信における送受信タイミン
グの位相関係を示す図である。マスタ側の送受信回路〕
10の送イ3タイミング位相τヮ70とすると、スlノ
ーブ側の送受信回路200の受信タイ、ミンク位相τ、
0は−rMT=Oで送出し人=パルス波形に対する最適
受信タイミングの遅延位相T1と伝送路遅延τ(d)の
和の位相τ、、、R−T1+τ(d)に定まる。スl/
−ブ側の送受信回路200の送信タイミ〉・り位相τs
1・はτS T ”τ5Iえである。マスタ側め送受信
回路11.0の受信タイミング位相τ閘、は同様に!−
てτMR=2(T、+τ(d))となる。FIG. 3 is a diagram showing the phase relationship of transmission and reception timing in normal digital communication. Master side transmitting/receiving circuit〕
Assuming that the transmission timing phase τ of 10 is 70, the reception tie of the transmission/reception circuit 200 on the slave side, the mink phase τ,
0 is determined by -rMT=O and the phase τ, which is the sum of the delay phase T1 of the optimal reception timing for the sender=pulse waveform and the transmission path delay τ(d), . Sl/
- Transmission timing of the transmitter/receiver circuit 200 on the side and phase τs
1 is τS T ”τ5I. Similarly, the reception timing phase τ of the transmitter/receiver circuit 11.0 on the master side is !-
Therefore, τMR=2(T,+τ(d)).
近年I SDNべ・−シックアクセス用エコーギャン七
う型伝送装置においては、タイ、ミンク位相調整のため
のf−1/・−=〉・グ時間が数秒へ数−4−秒ど長く
なっている。L述1.な従来の技術ては、特に送受信回
路の試験をテ・ス)へ用の送受信回路に引込んで接続す
る動作や、送信回路からの信号を回線5を通l−で自分
の受信回路に折返すようにループバック動作を行ったど
き、多数の回路を含むシステムでは]−回線ずつ順番に
行っていくため、その総試験時間が膨大となってし1う
という欠点がある。In recent years, the f-1/·-=〉·g time for tie and mink phase adjustment has increased from several seconds to several -4 seconds in the Echo Gyan-type transmission equipment for ISDN basic access. There is. L statement 1. Conventional technology involves the operation of connecting the transmitter/receiver circuit to the transmitter/receiver circuit, especially when testing the transmitter/receiver circuit, and the operation of returning the signal from the transmitter circuit to the own receiver circuit via line 5. When a loopback operation is performed in a system including a large number of circuits, the loopback operation is sequentially performed line by line, which has the disadvantage that the total test time becomes enormous.
本発明のディジタル信号送受信回路における受信タイミ
ング位相設定方式は 送信タイミングによって送信波形
を送り出す送信回路と受信タイミングによって受信信号
を打抜いて受信シンボルを復元する受信回路とを備える
2個のディジタル信号送受信回路の一方をマスタ側、他
方をス1=−ブ側どし、この両ディジタル信号送受信回
路間で回線を通して双方向通信を行うとき、前記スレー
ブ側で動作するディジタル信号送受信回路はその受信タ
イミングが送信タイミングより一定位相遅れるように構
成され、前記マスタ側で動作するディジタル信号送受信
回路ではその送信タイミングにりも前記一定位相互れた
位相からトレーニングを開始1またどきの受信タイミン
グが5自送信回路から前記回線を通−)で自受信回路へ
信号を折返すループバック式のテスI・の際に最適受信
タイミングとなり、且つ前記回線によるディジタル信号
の伝搬遅延時間が受信タイミングの位相を遅らせないよ
うな近距離条件で双方向通信を行う際にはマスタ側の最
適受信タイミングど一致するようにしたことを特徴とす
る。The receiving timing phase setting method in the digital signal transmitting/receiving circuit of the present invention includes two digital signal transmitting/receiving circuits including a transmitting circuit that sends out a transmitted waveform according to the transmitting timing, and a receiving circuit that punches out the received signal and restores the received symbol according to the receiving timing. One side is the master side and the other side is the slave side, and when two-way communication is performed through a line between these two digital signal transmitting/receiving circuits, the digital signal transmitting/receiving circuit operating on the slave side has its reception timing set to the transmit timing. The digital signal transmitting/receiving circuit, which is configured to be delayed by a certain phase from the timing, and which operates on the master side, also starts training from a phase that is a certain amount mutually different from the transmission timing. The optimal reception timing is obtained during the loopback type test I, which loops back the signal to the receiving circuit through the line (-), and the propagation delay of the digital signal through the line does not delay the phase of the reception timing. A feature is that when performing two-way communication under short-distance conditions, the optimum reception timing on the master side is matched.
r実施例〕 次に、本発明について図面を参照して説明する。r Example] Next, the present invention will be explained with reference to the drawings.
第1図は本発明の一実施例を示す送受信回路の回路図、
第2図は本発明の一実施例におく−iる送受信タイミミ
ングの位相関係を示す図である。FIG. 1 is a circuit diagram of a transmitting/receiving circuit showing an embodiment of the present invention;
FIG. 2 is a diagram showing the phase relationship of transmission and reception timing in an embodiment of the present invention.
第1図において送受信回路1. OOは送信回路]と、
受信回路2と、遅延回路3とを備え、遅延回路3は送信
タイミングt aの位相をそれぞれ遅延位相T1だけ遅
らせる。In FIG. 1, the transmitter/receiver circuit 1. OO is a transmitting circuit] and
It includes a receiving circuit 2 and a delay circuit 3, and the delay circuit 3 delays the phase of the transmission timing ta by a delay phase T1.
続いて本実施例の動作について第2図を使用して説明す
る。Next, the operation of this embodiment will be explained using FIG. 2.
第1図において、送信回路1は入力された送信シンボル
Aを送信タイミングtaUこよって送信信号Bに変換し
て出力する。一方受信回路2は相手送受信回路から受信
した受信信号Cを遅延回路3によって送信タイミングt
aより遅延位相T1t、5け遅れた受信タイミングtb
で打抜いて受信シンボルDを復元して出力する、
スレーブ側の送受信回路1.02の遅延回路3は常に固
定した遅延位相T1だけ遅らぜるよう動作するが、マス
タ側の送受信回路101の遅延回路3は受信タイミング
の)−レーニングの初期位相のみを遅延位相T1だけ遅
らせ、その後はスレーブ→マスタ方向の信号の最適受信
位相の引込むように動く。In FIG. 1, a transmitting circuit 1 converts an inputted transmitting symbol A into a transmitting signal B according to a transmitting timing taU and outputs the converted signal. On the other hand, the receiving circuit 2 transmits the received signal C received from the other party's transmitting/receiving circuit by the delay circuit 3 at the transmission timing t.
Delayed phase T1t, reception timing tb delayed by 5 orders of magnitude from a
The delay circuit 3 of the slave side transmitting/receiving circuit 1.02, which punches out the received symbol D and outputs it, always operates to delay by a fixed delay phase T1, but the master side transmitting/receiving circuit 101 The delay circuit 3 delays only the initial phase of ()-learning of the reception timing by a delay phase T1, and thereafter moves to bring in the optimum reception phase of the signal in the direction from slave to master.
これによって、マスタ、スレーブ側の送受信回路101
.102間で双方向通信を行うときの送受信タイミング
の位相関係は第2図のようになる。すなわち、第2図に
おいて、マスタ側の送受信回路101の送信タイミング
位相τMT=0とすると、スレーブ側の送受信回路10
2の受信タイミング位相τ5RはτMT=Oで送出した
パルス波形に対する最適受信タイミングの遅延位相T。As a result, the transmission/reception circuits 101 on the master and slave sides
.. The phase relationship of transmission and reception timing when bidirectional communication is performed between 102 is as shown in FIG. That is, in FIG. 2, if the transmission timing phase τMT of the master side transmitting/receiving circuit 101 is set to 0, then the slave side transmitting/receiving circuit 10
The reception timing phase τ5R of No. 2 is the delay phase T of the optimal reception timing with respect to the pulse waveform sent out when τMT=O.
と伝送路遅延τ(d)の和の位相τ5R=T1+τ(d
)に定まる。スレーブ側の送受信回路102の送信タイ
ミング位相τ5TはτST=τ(d)である。マスタ側
の送受信回路101の受信タイミング位相τMRは同様
にしてτMR= T 1+ 2で(d)となる。and the phase of the sum of the transmission path delay τ(d) τ5R=T1+τ(d
). The transmission timing phase τ5T of the transmission/reception circuit 102 on the slave side is τST=τ(d). Similarly, the reception timing phase τMR of the transmitting/receiving circuit 101 on the master side becomes (d) with τMR=T 1+2.
例えば、マスタ側のループバック時の最適受信タイミン
グは、伝送距離d=oのときのスレーブ側の最適受信タ
イミングτSRと同一であり位相T、である。従ってル
ープバック時に初期位相T1からトレーニングを開始す
ればトレーニング時間は著しく短くなる。For example, the optimum reception timing during loopback on the master side is the same as the optimum reception timing τSR on the slave side when the transmission distance d=o, and has a phase T. Therefore, if training is started from the initial phase T1 during loopback, the training time will be significantly shortened.
また、伝送距離d=oでマスタ、スレーブ側の送受信回
路101,102間で通信したときは、第2図よりマス
タ側の最適受信タイミングτMR”T、であるので、こ
のような場合に初期位相T1からトレーニングを開始す
ればトレーニング時間が著しく短くなる。Furthermore, when communication is carried out between the master and slave side transmitter/receiver circuits 101 and 102 at a transmission distance d=o, the optimum reception timing on the master side is τMR''T from FIG. 2, so in such a case, the initial phase If training starts from T1, the training time will be significantly shortened.
以上説明したように本発明は、送信タイミングから一定
位相だけ遅延させた最適受信タイミングでトレーニング
を開始するように位相調整したので、ループバックやテ
スト引込みによる送受信回路の試験時間を従来方式より
著しく短くできるとい−う効果を有する。As explained above, the present invention adjusts the phase so that training starts at the optimal reception timing that is delayed by a certain phase from the transmission timing, so the testing time of the transmission and reception circuits by loopback and test pull-in is significantly shorter than the conventional method. It has the effect of being able to.
第1図は本発明の一実施例を示す送受信回路の回路図、
第2図は本発明の一実施例における送受信タイミングの
位相関係を示す図、第3図は通常のディジタル通信にお
ける送受信タイミングの位相関係を示す図である。
1・・・送信回路、2・・・受信回路、3・・・遅延回
路、100.110,200・・・送受信回路、A・・
・送信シンボル、B・・・送信信号、C・・・受信信号
、D・・・受信シンボル、TI・・・遅延位相、Ta・
・・送信タイミング、tb・・・受信タイミング。FIG. 1 is a circuit diagram of a transmitting/receiving circuit showing an embodiment of the present invention;
FIG. 2 is a diagram showing the phase relationship between transmission and reception timings in an embodiment of the present invention, and FIG. 3 is a diagram showing the phase relationship between transmission and reception timings in normal digital communication. DESCRIPTION OF SYMBOLS 1... Transmission circuit, 2... Receiving circuit, 3... Delay circuit, 100.110,200... Transmitting/receiving circuit, A...
- Transmission symbol, B... Transmission signal, C... Reception signal, D... Reception symbol, TI... Delay phase, Ta.
...Transmission timing, tb...Reception timing.
Claims (1)
受信タイミングによって受信信号を打抜いて受信シンボ
ルを復元する受信回路とを備える2個のディジタル信号
送受信回路の一方をマスタ側、他方をスレーブ側とし、
この両ディジタル信号送受信回路間で回線を通して双方
向通信を行うとき、前記スレーブ側で動作するディジタ
ル信号送受信回路はその受信タイミングが送信タイミン
グより一定位相遅れるように構成され、前記マスタ側で
動作するディジタル信号送受信回路ではその送信タイミ
ングよりも前記一定位相遅れた位相からトレーニングを
開始したときの受信タイミングが、自送信回路から前記
回線を通って自受信回路へ信号を折返すループバック式
のテストの際に最適受信タイミングとなり、且つ前記回
線によるディジタル信号の伝搬遅延時間が受信タイミン
グの位相を遅らせないような近距離条件で双方向通信を
行う際にはマスタ側の最適受信タイミングと一致するよ
うにしたことを特徴とするディジタル信号送受信回路に
おける受信タイミング位相設定方式。Two digital signal transmitting/receiving circuits comprising a transmitting circuit that sends out a transmitted waveform according to the transmitting timing and a receiving circuit that punches out the received signal and restores the received symbol according to the receiving timing, one of which is a master side and the other is a slave side,
When bidirectional communication is performed between the two digital signal transmitting and receiving circuits through a line, the digital signal transmitting and receiving circuit operating on the slave side is configured so that its reception timing lags the transmission timing by a certain phase, and the digital signal transmitting and receiving circuit operating on the master side In the signal transmitting/receiving circuit, the receiving timing when training is started from a phase delayed by the fixed phase from the transmitting timing is determined during a loopback test in which the signal is looped back from the own transmitting circuit to the own receiving circuit through the line. When performing bidirectional communication under short-distance conditions where the propagation delay of the digital signal through the line does not delay the phase of the reception timing, the optimal reception timing is made to match the optimal reception timing on the master side. A receiving timing phase setting method in a digital signal transmitting/receiving circuit, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2082612A JPH03280739A (en) | 1990-03-29 | 1990-03-29 | Reception timing phase setting system in digital signal transmission and reception circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2082612A JPH03280739A (en) | 1990-03-29 | 1990-03-29 | Reception timing phase setting system in digital signal transmission and reception circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03280739A true JPH03280739A (en) | 1991-12-11 |
Family
ID=13779299
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2082612A Pending JPH03280739A (en) | 1990-03-29 | 1990-03-29 | Reception timing phase setting system in digital signal transmission and reception circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03280739A (en) |
-
1990
- 1990-03-29 JP JP2082612A patent/JPH03280739A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS62290260A (en) | Automatic switching system for data/sound transmission/ reception mode | |
| EP0268664B1 (en) | A method of coupling a data transmitter unit to a signal line and an apparatus for performing the invention | |
| JPH03280739A (en) | Reception timing phase setting system in digital signal transmission and reception circuit | |
| JP2003179584A (en) | How to synchronize network systems | |
| JPS58201440A (en) | Loop mode transmission system | |
| JPS5823984B2 (en) | Data signal transmission/reception method | |
| JPH03280742A (en) | Reception timing initial phase setting system in digital signal transmission and reception circuit | |
| JPH10262040A (en) | Synchronization method for data and transmitter and receiver for executing the method | |
| SU1707772A1 (en) | A repeater | |
| JPH09326817A (en) | Data transmitter for vehicle control | |
| JPS5962248A (en) | Bus system compensating delay amount | |
| JPH0370229A (en) | Data comparison synchronizing system serial communication system | |
| JPS63131641A (en) | Main station loopback test equipment | |
| JP2972244B2 (en) | Carrier sending level setting device | |
| JPH0472837A (en) | Data transmission delay adjustment system | |
| KR920005016B1 (en) | Loop back control circuit of universal signals transceiving circuit pack | |
| JP3440982B2 (en) | Digital signal transmission equipment | |
| RU1775868C (en) | Data transmission system | |
| JPH079466Y2 (en) | LAN interface | |
| RU2173026C2 (en) | Circuit delaying reference signal of synchronization from receiver of global satellite system of radio positioning, method of simultaneous transmission of search call | |
| CA2199647C (en) | Synchronization of communication devices connected over an asynchronous link | |
| JPS5836041A (en) | Interference prevention system for time division multidirectional multiplex communication | |
| JPH0323729A (en) | Bidirectional optical pcm transmitter | |
| JPH01174146A (en) | Radio communication equipment | |
| JPS6074851A (en) | Control system for synchronizing transmitter receiver |