JPH03282928A - Address control type information processor - Google Patents

Abstract

PURPOSE:To reduce the load of address calculation and to simultaneously execute the sequential processing and storage of many processing results by controlling the correction of an address by arithmetic operation based upon a required rule through an address control circuit arranged on the main storage side and using the corrected address as a processing result storing address. CONSTITUTION:An address storing data to be processed is calculated and set up in an address register 104 arranged on the CPU side and the data to be processed are fetched in a data register 108. After executing processing by an arithmetic circuit 107, the correction of the address such as simple shift, the insertion or correction of medium or lower bits, and the inversion of all bits or a part of bits is executed by an arithmetic circuit 105 in accordance with an instruction outputted from an instruction register 106 and the contents stored in the register 108 are stored in a main storage device 110 based upon the corrected address. This constitution makes it possible to reduce the number of hardwares for address calculation and time load and to simultaneously execute the sequential processing and storage of the many processing results of much data.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to an information processing device, and particularly when processing a large amount of processing objects and storing them.
The present invention relates to an information processing device equipped with a novel address calculation mechanism that significantly reduces the effort required to calculate addresses for storing processing results and the burden of bus design and operation.

(Prior Art and Problems to be Solved by the Invention) A conventional information processing device, like a computer whose block diagram is shown in FIG. 3 and whose operation is shown in FIG. counter) 310 and a data address register 304. In this information processing device, when an instruction is first fetched, and then an operand is fetched or a processing result is stored, the address where the instruction is stored, the address where the operand is stored, and the address where the processing result is stored are all In addition, calculations were performed each time according to instructions provided by software (programs). That is, when fetching an instruction, first calculate the address where the instruction is stored in step 433, set it in the instruction address register 310, and then perform the instruction fetch.If this instruction is an operand fetch instruction, In step 437, calculate the address, set it in the data address register 304, and transfer the data (operand) to the data register 304.
8 and stores the calculation result, the address to be stored is calculated in step 439 and set in the data address register 304, and the latest contents stored in the data register 308 are stored as data. bus 30
3 to the main storage device 301.

In the prior art, even in cases where the operation is similar to that described above and the address calculation is simpler, the calculation means is only provided as one of the machine language instructions. In other words, in a two-operand instruction, processing is performed at the address where one of the operands was stored.

For example, in the case of a machine language instruction that stores the summation results of two operands in an overlapping manner, there is no need to calculate the address where the processing results are stored, but the instruction itself can be read by fetching the instruction as described above. carried out,
Moreover, since the normal instruction is executed after this instruction is executed, it cannot be said that the effort of address calculation is particularly reduced overall.

As mentioned above, in conventional information processing devices, much of the valuable CPU time of the central processing unit is spent calculating addresses, steps 433,437°439 in FIG. The contents of the address bus that is externally output from the . There was a problem that the amount of power consumed increased.

Therefore, for example, in a communication network, we want to process a large amount of data, obtain a large amount of results, and store it almost in parallel with sequential processing, preferably in an extremely short time of about the time required for each processing time or less. If there is such a requirement, the conventional technology has no choice but to be completely inadequate.

If the addresses for storing the processing target and the processing result can be output using different buses, or in extreme cases, they are stored in different storage devices, then simply Parallelization is possible by having separate address calculation mechanisms for reading and storing.

However, especially when considering implementation using LSI, it is not realistic to more than double the bit width of the bus, and there are often constraints such as wanting to use the same bus and store the results in the same storage device.

It is an object of the present invention to reduce the burden of address calculation as much as possible, to store a large amount of processing results for a large amount of data in parallel almost at the same time as sequential processing, and to An object of the present invention is to provide an information processing device equipped with an address calculation mechanism that allows both a single main memory and a single main memory.

(Means for solving the problem) Solve the above problem. Therefore, the present invention is configured as follows.

That is, the present invention is composed of a main storage device that stores processing targets and processing results, and a central processing unit that performs necessary processing on the processing targets, and when the address where each processing target is stored is not modified at all. (1) simple shifts; (2) insertion or modification of upper, middle, or lower bits; (3) inversion of all or part of bits;
The present invention is characterized in that the result obtained by applying simple constraints such as combinations of 1), (2), and (3) is used as an address for storing the processing result.

(Embodiment) FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a flowchart showing its operation.

In this embodiment, the content of the process is transmitted in advance to the instruction register 106 in the central processing unit by an appropriate means, or the process target itself determines the process content based on the content of a specific field. It is a premise.

The operation of storing results while processing is performed as follows. First, in step 231 of FIG. 2, the address where the processing target is stored is calculated, this is set in the address register 104, and the processing target is fetched into the data register 108. After processing is performed by the arithmetic circuit 107 in the figure, this is shown in step 233, and the signal line 10 from the instruction register 106 is processed.
9, address control realized by the arithmetic circuit 105, i.e., (1) simple shift or (2) insertion or modification of upper, middle or lower bits, (3) all bits or Inversion of part of it,
(4) Create an address on the address bus 102 by performing simple control by combining the above (1), (2), and (3), and send it to the data register 108 via the data bus 103.
The processing results stored in are stored in the main storage device 101.

Specifically, to control the above address, for example, if the lower bits are inverted again, the processing target and processing result will be an even address,
It will be stored at an odd address, and if the upper bits are inverted again, the processing target and processing result will be stored in the first half of the main memory space,
It will be stored in the second half. In these cases, since the control is extremely simple, the signal line 109 from the instruction register 106 can be omitted.

The difference in size between the processing target and the processing result can be adjusted by the content of this control. In this case, it is natural that the fetching of the processing target and the storage of the processing results shown in Figure 2 are repeated over several steps as appropriate, but if the bus bandwidth is sufficient, both the fetching and storing can be done only once. You can also do it.

In an extreme case, if the processing target is lost and the size of the processing result is smaller than the processing target, the present invention stores the processing result as it is at the address where it was stored, without any control. This includes cases where it is not carried out.

When the present invention is implemented using an LSI, the dashed line 120 in FIG.
becomes a natural boundary. Since the address output from the register 104 can remain fixed until one processing target is read and the processing result is stored, it is possible to suppress an increase in power consumption due to changes in signal values. , address control signal line 109
often requires a very small bit width, so
The width of the address-related bus that exits the chip can also be kept small.

As a modification of the present invention, the address is controlled twice, and instead of giving instructions in advance as in the above embodiment, it is divided into three stages: fetching the instruction, fetching the processing target, and storing the processing result. It can be easily inferred that it is possible to perform these actions and expect similar effects.

(Effects of the Invention) As explained above, the present invention reduces the amount of hardware and time burden for address calculation, and allows processing results for a large amount of data to be processed easily.
Almost at the same time as sequential processing, store in parallel,
Moreover, it is possible to provide an information processing apparatus equipped with an address calculation mechanism that allows both the address bus and the main memory to remain single.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a flowchart showing its operation, FIG. 3 is a block diagram showing the prior art, and FIG. 4 is a flowchart showing its operation. 100... Processing content transmission means, 101, 301...
Main storage device, 102, 302 . . . address bus, 10
3.303...Data bus, 104...Address register, 105...Address control circuit, 106°30
6... Instruction register, 107, 307... Arithmetic circuit, 108, 308... Data register, 109...
- Address control signal line, 120, 320... Boundary between main memory and central processing unit, 304... Data address register, 310... Instruction address register, 31
1... Instruction address calculation circuit, 312... Data address calculation circuit.

Claims (1)

[Scope of Claims] A case in which a main storage device that stores processing targets and processing results and a central processing unit that performs necessary processing on the processing targets and does not modify the addresses where each processing target is stored at all. (1) simple shifts; (2) insertion or modification of upper, middle, or lower bits; (3) inversion of all or part of bits; or (4) (1) and (2) above. An address control type information processing device characterized in that the result obtained by performing simple control such as a combination of (3) and (3) is used as an address for storing a processing result.