JPH03282948A - Tag cache control circuit - Google Patents

Abstract

PURPOSE:To execute the parallel processing of an access from a CPU and an access from a memory bus and to prevent the generation of mutual delay between a cache hit and misdecision by constituting a tag memory of a dual port. CONSTITUTION:The tag memory 1 is constituted of the dual port and enabled to simultaneously read out a memory set address 210 controlled by a memory address input control circuit 5 and the tag address of a set selected by a CPU set address 212 controlled by a CPU address input control circuit 6 from two directions. There are two kinds of addresses, i.e. a CPU address inputted from the CPU and a memory address inputted from the memory bus. Only when a write access is generated and a read/write access is generated, an access control circuit 4 outputs a control signal 204 or 203.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to information processing devices, and in particular to tag cache control for determining cache hits/misses for cache accesses from a CPU and cache accesses from a memory bus. Regarding circuits.

[Prior art] Conventionally, there are CPU accesses and memory bus accesses to the cache, but since the tag memory has a single boat configuration, it can only accept access from either one, so access from one side is When an access occurs, the system always mediates with the access from the other party.

FIG. 3 is a block diagram of a conventional tag cache control circuit. Accesses from the CPU and the memory bus (memory read/write signal 101, CPU read/write signal 104) are arbitrated by the arbiter 23. Then, based on the arbitration result 301, the multiplexer 33 selects the memory tag address 105 or the CPU tag address 106.
The multiplexer 34 selects memory set address 02 or CPU set address 103. A tag address 304 is outputted from the tag memory 31 at the output 303 of the multiplexer 34, and this is compared with the output 302 of the multiplexer 33 by the hit determination circuit 32. If they match, a hit signal "305" is outputted.

[Problems to be Solved by the Invention] In the conventional tag cache control circuit described above, since the tag memory has a single boat configuration, it can only accept access from either the CPU access or the memory bus access. When access occurs from
This method always arbitrates with accesses from the other side, which has the disadvantage of mutually delaying accesses.

[Means for Solving the Problems] The tag cache control circuit of the present invention has a dual port configuration, and has a memory set address and C
A tag memory that can read the tag address of the set selected by the PU set address simultaneously from both directions, and inputs the CPU set address, memory set address, and tag memory read/write signals from the CPU and memory bus, and usually the CPU An access control signal and a memory access control signal are output, but only when accesses from the CPU and memory bus conflict, the CPU set address and memory set address match, and CPt
If the read/write signals from J and the memory bus are both read/write signals from the memory bus and the other is a read signal, the CPU access control signal or the memory access control signal arbitrates between the accesses from the CPU and the memory bus. An access control circuit that outputs a signal; a memory address input control circuit that outputs a memory set address and a memory read/write signal to the tag memory using a memory access control signal; and a memory address input control circuit that outputs a CPU set address and a CPU read/write signal using a CPU access control signal. a CPU address input control circuit that outputs the address to the tag memory; a memory hit determination circuit that compares the memory tag address input from the memory bus with the memory tag address output from the tag memory and performs a hit determination; It has a CPU hit determination circuit that compares the C P tJ tag address and the CPU tag address output from the tag memory and performs hit determination.

[Operation] By making the Kotag memory a dual port configuration,
Accesses from the CPU and accesses from the memory bus can be processed in parallel, and cache hit/miss determinations are not delayed.

[Embodiments] Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the tag cache control circuit of the present invention, showing only the portions related to the present invention.

The tag memory 1 has a dual port configuration, with a memory set address 210 controlled by a memory address input control circuit 5 and a CPU address input control circuit 6.
The set of tag addresses selected by the CPU set address 212 controlled by the CPU set address 212 can be read simultaneously from both directions.

Addresses include CPU addresses input from the CPU and memory addresses input from the memory bus. These addresses are classified into set addresses and tag addresses. Of these, the CPU set address 103 input from the CPU and the memory set address 102 input from the memory bus are input to the comparison circuit 2, and the comparison circuit 2 outputs the comparison result as a match signal 202. The read/write signals include a CPU read/write signal 104 input from the CPU and a memory read/write signal 101 input from the memory bus. A CPU read/write signal 104 and a memory read/write signal 101 are input to the arbiter 3. Arbiter 3 arbitrates between CPU access and memory bus access only when there is a conflict between write access from the CPU and memory bus, or when there is conflict between write access from one side of the CPU and memory bus and read access from the other. Result switching signal 201
Output as . The access control circuit 4 normally receives a CPU access control signal 204 and a memory access control signal 203.
However, according to the switching signal 201 and the coincidence signal 202, if a write access is occurring from either the CPU- or memory bus, and a read access or a write access is occurring from the other to the address of the write access. The CPU access control signal 204 or memory access control signal 203 is output only when The CPU address input control circuit 6 uses the CPU access control signal 204 to output the CPU set address 103 and the CPU leave/write signal 104 to signals 212 and 213, respectively, to control input to the tag memory 1. The memory address input control circuit 5 receives the memory access control signal 203
is used to output the memory set address 102 and memory read/write signal 101 to signals 210 and 211, respectively, to control input to the tag memory 1. Since the tag memory 1 has a dual port configuration, it can process CPU read access from the CPU and memory read access from the memory bus. At the time of CPU read, read access to tag memory 1 is started by CPU read/write signal 213, tag memory 1 selects a set by CPU set address 212, and outputs the tag address of the selected set as CPU tag address 206. . Furthermore, memory access can be processed in parallel with the CPU read access, and when reading memory, the read access is started by the memory read/write signal 211, and the tag memory 1 performs set selection by the memory set address 210. , set the tag address of the selected set to memory tag address 2
Output as 05. CPU hit determination circuit The CPU tag address 106 input from the CPU is compared with the CPU tag address 206 output from the tag memory 1, a hit determination is made, and a CPU hit signal 108 is output.

The memory hit determination circuit 8 compares the memory tag address 105 input from the memory bus with the memory tag address 205 output from the tag memory 1, performs a hit determination, and outputs a memory hit signal 107.

FIG. 2 is a block diagram of a second embodiment of the invention.

In this embodiment, a comparison circuit is not used, and the CPU access switching signal 222 and memory access switching signal 221, which are output signals from the arbiter 13, are input to the CPLI address input control circuit 6 and the memory address input control circuit 5, respectively. .

The second embodiment has the advantage that when there is a high possibility that the CPU address and the memory address are the same, a delay due to the comparator circuit 2 and the access control circuit 4 does not occur, so that higher-speed processing is possible.

[Effects of the Invention] As explained above, the present invention has a tag memory with a dual port configuration, so that processing can be executed in parallel without delaying CPU access and memory bus access, and each access This has the effect of speeding up processing.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention, FIG. 2 is a block diagram of a second embodiment of the present invention, and FIG. 3 is a block diagram of a conventional example. DESCRIPTION OF SYMBOLS 1... Tag memory, 2... Comparison circuit, 3, 13.23... Arbiter, 4... Access control circuit, 5... Memory address input control circuit, 6... CPU
Address input control circuit, 7... CPU hit determination circuit, 8... Memory hit determination circuit, 01, 211... Memory read/write signal, 02
, 210...Memory set address, 03, 21
2...CPU set address, 04, 213...
CPU read/write signal, 05...Memory tag address, 06...CPU tag address, 107...Memory hit signal, 108...CPU hit signal, 201, 301...Switching signal, 202... Coincidence signal, 203...Memory access control signal, 204.=cp
u access control signal, 205... memory tag address output signal, 206...
- CPU tag address output signal, 32... Hit determination circuit, 33, 34... Multiplexer, 302... Tag address, 303... Set address, 304... Tag address output signal.

Claims (1)

[Claims] 1. A tag cache control circuit that determines cache hit/miss with respect to cache access from a CPU and a cache access from a memory bus, which has a dual port configuration and has a memory set address and a memory bus.
A tag memory that can read the tag address of the set selected by the PU set address simultaneously from both directions, and inputs the CPU set address, memory set address, and tag memory read/write signals from the CPU and memory bus, and usually the CPU An access control signal and a memory access control signal are output, but only when accesses from the CPU and memory bus conflict, the CPU set address and memory set address match, and the CPU
If the read/write signals from the CPU and memory bus are both write signals, or if one is a write signal and the other is a read signal, the CPU arbitrates between accesses from the CPU and the memory bus,
an access control circuit that outputs a PU access control signal or a memory access control signal; a memory address input control circuit that outputs a memory set address and a memory read/write signal to the tag memory using the memory access control signal; A CPU address input control circuit that outputs the set address and CPU read/write signals to the tag memory, and a memory hit that compares the memory tag address input from the memory bus with the memory tag address output from the tag memory to determine a hit. A tag cache control circuit comprising a determination circuit and a CPU hit determination circuit that compares a CPU tag address input from a CPU with a CPU tag address output from a tag memory to determine a hit.