JPH0328736U - - Google Patents
Info
- Publication number
- JPH0328736U JPH0328736U JP8931689U JP8931689U JPH0328736U JP H0328736 U JPH0328736 U JP H0328736U JP 8931689 U JP8931689 U JP 8931689U JP 8931689 U JP8931689 U JP 8931689U JP H0328736 U JPH0328736 U JP H0328736U
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- side power
- potential side
- supply wiring
- regions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Description
第１図は本考案の第１の実施例を示すレイアウ
ト図、第２図はＩ／Ｏバツフア配置状態の説明を
するための平面模式図、第３図は第２の実施例を
示すレイアウト図、第４図は従来例を示すレイア
ウト図である。
１０……半導体チツプ、１１−１〜１１−８…
…分割可能領域、１２，１２−１，１２−２，…
，……Ｉ／Ｏバツフア領域、１３……Ｉ／Ｏバツ
フアのボンデイングパツド、１４……内部ゲート
領域、２１−１〜２１−４……コーナー部の分割
可能領域。
Fig. 1 is a layout diagram showing a first embodiment of the present invention, Fig. 2 is a schematic plan view for explaining the I/O buffer arrangement state, and Fig. 3 is a layout diagram showing a second embodiment. , FIG. 4 is a layout diagram showing a conventional example. 10...Semiconductor chips, 11-1 to 11-8...
...dividable area, 12, 12-1, 12-2,...
,... I/O buffer area, 13... I/O buffer bonding pad, 14... internal gate area, 21-1 to 21-4... corner part divisible area.
Claims (1)
域を配設し、これらに共通に高電位側電源配線及
び低電位側電源配線を配設したゲートアレイ型半
導体集積回路装置において、前記低電位側電源配
線には、その箇所にコンタクト又はスルーホール
を設けていない分割可能領域が複数個設けられそ
のうち少なくとも１つでは配線層が除去されて前
記低電位側電源配線が分割されていることを特徴
とするゲートアレイ型半導体集積回路装置。 In a gate array type semiconductor integrated circuit device in which a large number of input/output buffer regions are arranged around a semiconductor chip, and a high potential side power supply wiring and a low potential side power supply wiring are arranged in common to these areas, the low potential side power supply wiring The gate is characterized in that a plurality of divisible regions are provided in which no contacts or through holes are provided, and the wiring layer is removed in at least one of the regions, and the low potential side power supply wiring is divided. Array type semiconductor integrated circuit device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8931689U JPH0328736U (en) | 1989-07-28 | 1989-07-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8931689U JPH0328736U (en) | 1989-07-28 | 1989-07-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0328736U true JPH0328736U (en) | 1991-03-22 |
Family
ID=31638899
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8931689U Pending JPH0328736U (en) | 1989-07-28 | 1989-07-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0328736U (en) |
-
1989
- 1989-07-28 JP JP8931689U patent/JPH0328736U/ja active Pending
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