JPH0430730U - - Google Patents
Info
- Publication number
- JPH0430730U JPH0430730U JP7250590U JP7250590U JPH0430730U JP H0430730 U JPH0430730 U JP H0430730U JP 7250590 U JP7250590 U JP 7250590U JP 7250590 U JP7250590 U JP 7250590U JP H0430730 U JPH0430730 U JP H0430730U
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- semiconductor integrated
- integrated circuit
- chip
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 12
- 230000002093 peripheral effect Effects 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Description
第１図はこの考案の一実施例である半導体集積
回路の平面図、第２図、第３図はこの考案の他の
実施例を示す半導体集積回路の平面図、第４図は
この考案によつて得られた中間配線層の等価回路
の回路図、第５図、第６図はクロストーク現象を
説明するための説明図、第７図は従来の半導体集
積回路の平面図である。
図において、１は半導体集積回路チツプ、２は
周辺端子、３は電源端子、４は接地端子、５はバ
ツフア回路セル、６は内部回路レイアウトパター
ン、７は上層配線、１０は中間配線層を示す。な
お、図中、同一符号は同一、又は相当部分を示す
。
Fig. 1 is a plan view of a semiconductor integrated circuit that is an embodiment of this invention, Figs. 2 and 3 are plan views of a semiconductor integrated circuit that shows other embodiments of this invention, and Fig. 4 is a plan view of a semiconductor integrated circuit that is an embodiment of this invention. 5 and 6 are explanatory diagrams for explaining the crosstalk phenomenon, and FIG. 7 is a plan view of a conventional semiconductor integrated circuit. In the figure, 1 is a semiconductor integrated circuit chip, 2 is a peripheral terminal, 3 is a power supply terminal, 4 is a ground terminal, 5 is a buffer circuit cell, 6 is an internal circuit layout pattern, 7 is an upper layer wiring, and 10 is an intermediate wiring layer. . In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
補正 平２．１１．６
実用新案登録請求の範囲を次のように補正する
。Amendment 2.11.6. The scope of claims for utility model registration is amended as follows.
【実用新案登録請求の範囲】
半導体集積回路チツプの外部より半導体集積回
路チツプの周辺端子部分を経由し、バツフア回路
を介さないで直接多層配線における上層配線層を
用いて、チツプ内部の回路まで配線される、ある
いは半導体集積回路チツプ上を通り抜け他の辺あ
るいは同一辺の周辺端子まで配線される場合、そ
の配線の下層に存在する各種素子あるいは配線と
の間に必らず電源電位あるいは接地電位が印加さ
れた中間層配線を設けた部分を少なくとも含んだ
ことを特徴とする半導体集積回路。[Claim for Utility Model Registration] Wiring from the outside of the semiconductor integrated circuit chip via the peripheral terminals of the semiconductor integrated circuit chip, directly to the circuit inside the chip using the upper wiring layer of multilayer wiring without going through a buffer circuit. When the wiring is routed through a semiconductor integrated circuit chip to a peripheral terminal on another side or on the same side , there must be gaps between the wiring and the various elements or wiring that exist in the underlying layer. A semiconductor integrated circuit comprising at least a portion provided with an intermediate layer wiring to which a power supply potential or a ground potential is applied.
Claims (1)
路チツプの周辺端子部分を経由し、バツフア回路
を介さないで直接多層配線における上層配線層を
用いて、チツプ内部の回路まで配線される、ある
いは半導体集積回路チツプ上を通り抜け他の辺の
周辺端子まで配線される場合、その配線の下層に
存在する各種素子あるいは配線との間に必らず電
源電位あるいは接地電位が印加された中間層配線
を設けた部分を少なくとも含んだことを特徴とす
る半導体集積回路。 Wiring is performed from outside the semiconductor integrated circuit chip via the peripheral terminals of the semiconductor integrated circuit chip, directly to the internal circuitry of the chip using the upper wiring layer of the multilayer wiring without going through a buffer circuit, or to the circuit inside the chip. When wiring passes through the top and reaches peripheral terminals on other sides, there must be an intermediate layer wiring to which a power supply potential or ground potential is applied between the wiring and various elements or wiring existing in the layer below the wiring. A semiconductor integrated circuit characterized by comprising at least:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7250590U JPH0430730U (en) | 1990-07-05 | 1990-07-05 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7250590U JPH0430730U (en) | 1990-07-05 | 1990-07-05 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0430730U true JPH0430730U (en) | 1992-03-12 |
Family
ID=31610498
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7250590U Pending JPH0430730U (en) | 1990-07-05 | 1990-07-05 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0430730U (en) |
-
1990
- 1990-07-05 JP JP7250590U patent/JPH0430730U/ja active Pending
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