JPH0328754U - - Google Patents
Info
- Publication number
- JPH0328754U JPH0328754U JP1989089705U JP8970589U JPH0328754U JP H0328754 U JPH0328754 U JP H0328754U JP 1989089705 U JP1989089705 U JP 1989089705U JP 8970589 U JP8970589 U JP 8970589U JP H0328754 U JPH0328754 U JP H0328754U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- island
- lead frame
- frame
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/581—Auxiliary members, e.g. flow barriers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
第１図ａ，ｂは本考案の一実施例の平面図及び
Ａ−Ａ′線断面図、第２図は第１図ａ，ｂのリー
ドフレームに半導体素子を搭載した断面図、第３
図は従来のリードフレームの一例の断面図である
。 １……アイランド、２……枠、３……リード端
子、４……半導体チツプ、５……金属細線。
Ａ−Ａ′線断面図、第２図は第１図ａ，ｂのリー
ドフレームに半導体素子を搭載した断面図、第３
図は従来のリードフレームの一例の断面図である
。 １……アイランド、２……枠、３……リード端
子、４……半導体チツプ、５……金属細線。
Claims (1)
- 半導体チツプを搭載するアイランドと、前記半
導体チツプの電極に接続し外部へ導出されるリー
ド端子とを有するリードフレームにおいて、前記
アイランドの周囲に前記半導体チツプの厚さより
も高い枠を設けたことを特徴とするリードフレー
ム。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989089705U JPH0328754U (ja) | 1989-07-28 | 1989-07-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989089705U JPH0328754U (ja) | 1989-07-28 | 1989-07-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0328754U true JPH0328754U (ja) | 1991-03-22 |
Family
ID=31639274
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989089705U Pending JPH0328754U (ja) | 1989-07-28 | 1989-07-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0328754U (ja) |
-
1989
- 1989-07-28 JP JP1989089705U patent/JPH0328754U/ja active Pending