JPH03291740A - Memory controller - Google Patents

Abstract

PURPOSE:To enable processing with the same number of cycles as in the case of byte access even when a memory access unit is made larger than a byte unit by enabling access to plural memories with one address data and switching a data bus corresponding to the access size of the memory. CONSTITUTION:Address data A0-A15 to be sent from an address counter not shown in the figure through a bus AB are inputted to a gate circuit 11 for word access, and the data A1-A15 excepting for the least significant bit A0 are inputted to a gate circuit 12 for byte access. The least significant bit A0 is inputted to a NOR circuit 13 and inputted through an inverter 14 to a NOR circuit 15 and further, a byte/word switching signal B/W to be sent from a control circuit not shown in the figure is inputted to NOR circuits 13 and 14, directly inputted through an output control terminal the inverse of OC of the circuit 11 and inputted to a terminal the inverse of OC of the circuit 12 as well. Afterwards, outputs are respectively applied to a high-order side RAM 17 and a low-order side RAM 18.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory control device in a microprogram type data processing device.

[Summary of the Invention] The memory control device of the present invention includes a plurality of memories, for example, two memories, and accesses the two memories alternately during byte transfer, and simultaneously accesses both memories during word transfer. This allows byte access and word access to be executed in the same number of cycles.

[Prior Art] Conventionally, a memory control device used in a data processing device such as a personal computer has a one-to-one correspondence between a physical memory and its address, and accesses are performed in units of access, such as bytes or words. As the unit size increases, the number of cycles to memory increases accordingly.

[Problems to be Solved by the Invention] As described above, the conventional memory control device has a problem in that as the access unit becomes larger, the number of cycles increases and the time required to access the memory becomes longer. Ta. Further, as the capacity of the memory space increases, the size of the address counter (address register) has to be increased by a factor of 2, such as 8 bits, 16 bits, or 32 bits.

This kind of cause causes physical memory and its address to be
This is thought to be due to the one-to-one correspondence.

If we make it possible to address multiple memories with one address data and switch the data bus according to the memory access unit, the number of cycles can be reduced even if the memory access unit becomes large. It is clear that there is no need to increase the size of the address counter, and even if the capacity of the memory space is increased by one, there is no need to increase the size of the address counter.

An object of the present invention is to provide a memory control device in which the number of cycles does not increase even if the memory access unit becomes large, and there is no need to increase the size of the address counter even if the capacity of the memory space increases. That's true.

[Means to solve the problem] The means of the present invention are as follows.

(1) Address counter.

For example, it is a counter that specifies a memory address.

(2) 2n memories.

For example, it is a plurality of memories for storing data, such as RAM.

(3) A first address supply means for supplying to each memory an address obtained by shifting out the original address by n bits downwards every time an address is generated during a byte access.

For example, it is a gate circuit 12 that specifies a memory address based on address data and a bank switching signal output from the address counter.

(4) A second address supply means for supplying an original address to each memory each time an address is generated during word access.

For example, a gate circuit that specifies a memory address using address data output from the above address counter]
It is 1.

(5) Selection means that sequentially selects memories corresponding to the shifted-out n-bit data content in a byte access each time an address is generated, and selects all memories at the same time in a word access.

For example, it is a circuit composed of an inverter 4, a NOR circuit 13.1.5, etc., which selects and specifies the memory according to the least significant bit of address data sent from the address counter.

(6) Output means that outputs data in byte units for each address generation during byte access, and outputs data in 2n byte units for each address generation during word access.

For example, gate circuits 19 and 20 are provided on the data output side of the memory and output data in response to a byte/word switching signal.

[Effect] The operation of the means of the invention is as follows.

When a byte access is specified by the byte/word switching signal, a memory address is specified by the first addressing means. At this time, the memory corresponding to the shifted-out n-bit data is sequentially selected by the selection means every time an address is generated, and the stored data is read out.

The data read from this memory is sent by the byte unit to the byte processing device by the output means each time an address is generated.

Further, when word access is designated by the byte/word switching signal, the memory address is designated by the second addressing means. At this time, all the memories are simultaneously selected by the selection means and the stored data is read out. The data read from this memory is sent to the word processing device by the output means in units of 2n bytes every time an address is generated.

[Example] Hereinafter, an example will be described with reference to FIGS. 1 to 3.

In Figures 1 to 3, the data size is 8 bits and 64
This example shows an example in which two memories each having a memory space of bytes are used.

FIG. 1 is a block diagram showing a memory control device according to an embodiment. The 16-bit address data AO to AL5 sent from the address counter (not shown) via the address bus AB are inputted to the gate circuit 11 for word access, and are inputted to the gate circuit 11 for word access. 15
Bit data AL-AI5 is input to the gate circuit 12 for byte access. The least significant bit AO is input to the NOR circuit 13 and also to the NOR circuit 5 via the inverter 14. The above NOR circuit 1B, 1.
4 further receives a byte/word switching signal B/W sent from a control section (not shown). Further, this byte/word switching signal B//W is input to the output control terminal OC of the gate circuit 11 via the inverter 16 and directly to the output control terminal OC of the gate circuit 12.

[Above gate circuit] When a "0" signal is given to the output control terminal OC, the gate circuit 1 directly receives address data AO to A15 sent from the address bus AB to PAO to PA]
5 as upper (H) side RAM 17 and lower (L) side RA
Output to the address terminal of M18. above RAM], 7.
18 has, for example, a data size of 8 bits and a memory space of 64 bytes. On the other hand, the gate circuit 12 is
Address data A1 sent by data bus AB
~Shift A14 to the lower side by 1 bit and set PAO~PA
], 4, and outputs the bank switching signal BC sent from the control section as the most significant bit signal PA15. This bank switching signal BC is specified by an instruction according to the progress of the program, for example. Address data PAO to PA output from the gate circuit 2
]5 is input to the address terminal of RAM17.18.

NOR circuit 15 is connected to chip select terminal C8 of RAM17.
The output signal of the NOR circuit 16 is input to the chip select terminal C5 of the RAM 18.

The data terminals DO to D7 of the RAM 17 are connected to the data terminals D8 to D15 of the upper gate circuit 9 and the lower gate circuit 20 via the data bus DBI. Furthermore, the data terminals DO to D7 of the RAM 18 are
It is connected to data terminals DO to D7 of gate circuits 19.20 via data bus DB2. In addition, the gate circuit 19
is connected to a word processing device (not shown) via a 16-bit (word) data bus DB-A, and the gate circuit 20 is connected to a byte processing device (not shown) via an 8-bit (byte) data bus DB-B. (not shown). The gate circuit 20 has a switching function, and the NOR circuit 13
．． One of the data buses DBI and DB2 is selected by a signal from 15.

For example, if the signal from the NOR circuit 15 is “0”, the NOR circuit] 3
When the signal from the NOR circuit 15 is "1", the data bus DBl side is selected and connected to the data bus DB-B, and when the signal from the NOR circuit 15 is "1" or the signal from the NOR circuit 13 is "ON", the data bus DB2 side is selected. Select and connect to data bus DB-B. Furthermore, the byte/word switching signal B/W is connected to the output control terminal OC of one of the gate circuits through the inverter 21.
is input via the output control terminal OC of the gate circuit 20.
The byte/word switching signal B/W is directly input manually. The gate circuits 19 and 20 are turned off when the byte/word switching signal B/W is "1" and turned on when it is "0".

FIG. 2 shows the address setting state and data storage state of the RAMs 17 and 18.

RAM17.18 is r 0000 (I□,''~rF
It has an address of FFFu++J, for example r0
000+u+J ~ "BFFFtu+J area is byte transfer area BA, rcOOOtH+J ~ rFFFFtH+J
The area is the word transfer area WA. Also, R.A.
For example, in M1.7.18, the area from 0 roooo (old) to r7FFF, +++J is set to bank #0, and the area from r8000 (old) to FFFF+o+J is set to bank #1.Then, byte transfer area BA In this case, RAMs 17 and 18 are accessed alternately, and RAM 1718 is accessed simultaneously in the word transfer area.

The operation of the above embodiment will be explained below with reference to the timing chart of FIG.

Now, if the byte processing device updates the storage contents of the byte transfer area BA of RAM 17.18 from the start address, the byte/
"O" is given as the word switching signal B/W, and "0" is given as the bank switching signal BC. When "0" is applied as the byte/word switching signal B/W, the output control terminal OC of the gate circuit 11 becomes "1" and the output control terminal OC of the gate circuit 12 becomes "0".

Therefore, the gate circuit 11 is turned off and the gate circuit 12 is turned on.

In this state, when the start address r0000j is sent from the address counter as address data 1] AO~AI5, A1-A1.5 of this address data is sent.
passes through the gate circuit 12, is shifted downward by one bit, and is output as PAO-PA1,4. At this time, bank switching signal BC (“0”) is sent from gate circuit 12 to PA.
It is output as l5. As a result, when the first address is sent from the address counter, the gate circuit 12 outputs all "O" as address pigeons PAO to PA15.
The address of exactly ro 000J is output. At this time, the least significant bit AO of address data AO-Ai5 is “
0'', and the byte/word switching signal B/W is 0.
'', the output of the NOR circuit 15 becomes ``O'', and the output of the NOR circuit 3 becomes 1'', and the RAM 1.7 on the upper side becomes enabled. As a result, the start address r0000J of the RAM 17 is designated, and the stored data is read out and input to the get circuits 19 and 20.

In this case, since the byte/word switching signal B/W is "0", the gate circuit 19 is held in the OFF]2 state and the gate circuit 20 is held in the ON state. The gate circuit 20 performs a switching operation according to the outputs of the NOR circuits 13 and 15, but at this time, the output of the NOR circuit 15 is "0".
Since the output of the NOR circuit 13 is “1”, the RAM
17 is selected and transferred to the byte processing device via the 8-bit data bus DB-B.

Next, address data r0001 is obtained from the address counter.
When J is sent, the least significant bit AO is "1", so the output of the NOR circuit 15 is "]", the output of the NOR circuit 13 is "0", and the lower RAM 1.8 is enabled. state. At this time, the address data PAL to PA15 output from the gate circuit 12 do not change, and r
o It is held at 000J. Therefore, the start address r0000j of the RAM 18 is designated, and the stored data is read out and sent to the gate circuit 20. At this time, the output of the NOR circuit 15 is "1" and the output of the NOR circuit 13 is "0".
", so the gate circuit 20 is RAM 1.
8 read data is selected and transferred to the byte processing device via the 8-bit data bus DB-B.

Next, when address data r0002J is sent,
Since the least significant bit AO is "0", the output of the NOR circuit 15 is "0" and the output of the NOR circuit 13 is "1", and the upper RAM 17 is enabled. At this time, address data PAI to PA output from the gate circuit 12
I5 changes to r 000 ], J. Therefore, R
Address r 0001 J of AM18 is specified and its stored data is read. Thereafter, similar operations are repeated, and the RAMs 17 and 18 are alternately accessed to read out the stored data and transferred to the byte processing device via the data bus DB-B.

After that, when the processing is completed up to the address rF F F Or will be sent. When the bank switching signal BC is switched to high level]4, the gate circuit 12 outputs P
AI5 becomes 1". Therefore, from gate circuit ]2,
r8000J address data is output. Further, when the least significant bit AO of the address data is "0", the upper RAM 17 is enabled as described above, so the address r8000J of the RAM 17, that is, the start address of Banks #] is specified and the memory is Data is read. The read data from the RAM 17 is sent from the gate circuit 20 to the byte processing device via the data bus DB-B.

Next, address data ro001 is obtained from the address counter.
When J is sent, the RAM1 on the lower side is
8 is in the enabled state.

At this time, the address data PAI-PA]5 output from the gate circuit 12 does not change and is held at r8000J. Therefore, address r8000J of RAM]8,
That is, the start address of bank #1 is designated and its stored data is read out. The read data from the RAM 18 is sent from the 5G I circuit 20 to the byte processing device via the data bus DB-B.

Thereafter, similar operations are repeated up to address r7FFFJ of RAM 17.18, that is, the final address of byte transfer area BA.

Next, the operation when performing word transfer will be explained.

When performing word transfer, "1" is given as the byte/word switching signal B/W from the control section, and rCO00J is given as the address data. In this case, the level of bank switching signal BC is not particularly limited.

When "1" is applied as the byte/word switching signal B/W, the output of the inverter 16.21 becomes MO", and the gate circuits 11..19 are turned on.

At this time, the gate circuit 12.20 is switched from the on state to the off state. Also, the byte/word switching signal B/
When W is "1", both the outputs of the NOR circuits 15 and 13 become "0", and both the RAMs 17 and 18 are enabled.

When the above gate circuit [1] turns on, the address data rCO0 sent from the address counter [6]
0J is output as is as PAO~PAI5, and RA
The addresses of M17 and RAM18 are specified. Therefore,
From the RAMs 17 and 18, 8-bit data stored at the same address rCOOOJ is read out and input to the gate circuit 19. At this time, the read data of the RAM 17 is sent to terminals D8 to D15 on the upper bit side of one gate circuit.
The data read from the RAM 18 is input to terminals DO to D7 on the lower bit side of one gate circuit. Therefore, 8 read from RAM], 7, 1.8, respectively.
The bit data is synthesized into 16-bit data DO to D15 by one gate circuit, and then transferred to the 16-bit data bus D.
It is sent to the word processing device via B-A.

Thereafter, each time the address data from the address counter is updated in the same way, 8-bit data corresponding to the specified address is read from both RAMs 17 and 18, synthesized into 16-bit data by the gate circuit 9, and then sent to the data bus. It is sent to the word processing device via DB-A.

As mentioned above, by the byte/word switching signal B/W, the R
AM], 7.18, byte transfer processing and word transfer processing are switched, and word access can be processed in the same number of cycles as byte access. Also, a 16-bit address counter can cover 1.28 bytes of memory space.

The following describes the operation when reading data stored in RAM 1.7.18 to the processing device, but when writing data processed by the data processing device to RAM 17. It is done in the same way.

In the above embodiment, a case is shown in which byte access and word access are combined, but the present invention can also be applied to a combination with longword (4-byte) access. That is, these are combinations of ■byte and longword, ■word and longword, ■byte, word, longword, ]8. In this case, in ■, specify the bank as 2.
Make it bit. In addition, in case of (1), it is sufficient to prepare two bits for specifying the bank and two bits for the word.

[Effects of the Invention] As described in detail above, according to the present invention, even if the memory access unit becomes larger than the byte unit, it can be processed in the same number of cycles as byte access, and the processing speed can be significantly improved. Furthermore, even if the size of the address counter is the same as before, the memory space can be increased several times.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a circuit configuration of a memory control device according to an embodiment of the present invention, FIG. 2 is a diagram showing a memory storage structure of a memory in the same embodiment, and FIG. 3 explains the operation of the same embodiment. This is a timing chart for 11.12...Gate circuit, 13.15 NOR circuit, 1
4... Inverter, 16 N... Inverter, 1718
...RAM, 19.20...gate circuit. 9 8-point 384 JP-A-3 291740 (9)

Claims (1)

[Claims] An address counter, 2^n memories, and an original address that converts the original address by n each time an address is generated during byte access.
a first address supply means for supplying an address shifted out to the lower bits to each memory; a second address supply means for supplying an original address to each memory each time an address is generated during word access; has a selection means that sequentially selects the memory corresponding to the n-bit data content shifted out each time an address is generated, and selects all memories at the same time during word access, and a selection means that selects the memory corresponding to the shifted out n-bit data content at the same time at each address generation. 1. A memory control device comprising: output means for outputting data in units of 2^n bytes each time an address is generated during word access.