JPH03185536A - Memory addressing system for microcomputer - Google Patents

Abstract

PURPOSE:To eliminate the need for the frequently switching of memory bank specification at the time of executing exchanging, transfer or comparing operation of the data between different memory banks by providing the memory addressing system with a means for selecting accessible indirect addressing for a memory bank selected by a memory bank selecting register. CONSTITUTION:An exchange instruction between an accumulator and a memory for a memory bank selected by the memory bank selecting register 5 is issued with indirect addressing to an H/L register 1, and then the exchange instruction between the accumulator and the memory is issued by indirect addressing to a D/E register 2 without changing the contents of the register 5. Then the exchange instruction between the accumulator and memory is issued again by the indirect addressing to the H/L register 1. Consequently, the contents stored in the memory bank specified by the register 5 can be exchanged with the contents stored in a memory bank 0 and it is unnecessary to change the contents of the register 5 during the exchange.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory addressing method for a microcomputer, and more particularly to a memory addressing method for a microcomputer having a memory space constituted by a plurality of memory banks.

[Conventional technology]

In conventional microcomputers, for example, 4-bit single-chip microcomputers, in addition to direct addressing, which is directly specified with an instruction word, there are two ways to read/write data to a predetermined address in the built-in data memory: a 4-bit register. There is register indirect addressing in which the 8-bit content of the HL register is used as a bare address, such as bare H and L registers. In many cases, multiple sets of 8-bit registers used for this indirect addressing, such as HL register and DB register, are prepared.

In such register indirect addressing, if the data memory capacity is within the range of 256 addresses, it is possible to indirectly address all addresses with 8-bit contents using 4-bit registers as bare. If you try to incorporate a data memory capacity that exceeds the 256 address range, register indirect addressing is not possible for all data memories as is, so,
As a method to deal with the second issue, the entire data memory space is divided into multiple data memory spaces (hereinafter referred to as memory banks) each consisting of data memory spaces that allow conventional register indirect addressing. There is a method of selecting a target memory bank and indirectly addressing the data memory space within the selected memory bank using the bare register.

For example, a data memory consisting of an address space of 0 to 1023023 is divided into 4 memory banks of 256 addresses each, and a register for selecting the memory bank, that is, a 2-bit register in the case of 4 memory banks, is provided. By doing so, the above 8
Indirect addressing can be done using bit bare registers.

When changing the four memory banks from memory bank 0 to memory bank 3 and exchanging the contents of the specified address of memory bank l and the contents of the specified address of memory puncture 00 by register indirect addressing, write the contents of memory bank 1 in the HL register. Set 8-bit data that specifies the address of
Also, 8-bit data specifying an address in memory bank 0 is set in the DE register. First, 2-bit data specifying memory bank 1 is written into the memory bank select register, and the contents of a predetermined address in memory bank 1 and the 7 cumulator are exchanged by HL register indirect addressing. Thereafter, data specifying memory bank 0 is written to the memory bank select register, and the contents of the accumulator and the predetermined location in memory bank 0 are exchanged by DE register indirect addressing. Furthermore, mail again
The data in memory bank 1 and the data in memory bank 0 are exchanged by specifying V /< link 1 and exchanging the contents of the accumulator and the predetermined location in the memory bank l by HL register indirect addressing. be able to.

[Problem to be solved by the invention]

In the conventional microcomputer memory addressing method described above, when operations such as exchanging data or comparing data between memory banks are frequently performed, it is necessary to switch memory banks frequently, which increases the number of program steps. Even if you create a subroutine to reduce the number of steps, data processing time will increase due to memory bank switching operations when the above operations are performed many times over a wide range of addresses. There is a drawback that it does.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory addressing system for a microcomputer that can reduce the number of program steps and data processing time.

[Means to solve the problem]

The memory addressing method of the microcomputer of the present invention includes a plurality of memory banks in which the memory space is divided;
In a memory addressing system for a microcomputer, the microcomputer has a memory bank select register that specifies one of the memory banks, and addressing means that indirectly specifies a memory address within the memory bank. , a lower address selection switching circuit that specifies one of the plurality of indirect addressing registers using an instruction code of an indirect addressing instruction and outputs it as part of a memory address;
an effective register selection register that specifies indirect addressing that is valid for the memory bank specified by the memory bank select register; and an upper address selection switching circuit that switches whether or not to output the contents as an upper memory address.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a memory addressing system of a microcomputer showing a first embodiment of the present invention.

As shown in FIG. 1, this embodiment uses a 4-bit register H
and register L, an 8-bit HL register 1 for indirect addressing, and a 4-bit register D.
8-bit DE register 2 for indirect addressing formed as a pair of and register E, and 4-bit register B
8 bits for indirect addressing formed as a pair of y) BC register 3 and register C, and 2 bits) rl and rO that specify one of the three 8-bit registers in the instruction code of the indirect addressing instruction. Select one of the contents of HL register 1, DE register 2, or BC register 3, and select the lower 8 bits of the memory address) MA7~
a lower address selection switching circuit 4 outputting as MAO;
A 2-bit memory bank select register 5 is used to specify one of multiple memory banks, and when an indirect addressing instruction is executed, indirect addressing is enabled for the memory bank selected by the memory bank select register 5. An effective register selection register 6 selects a register for indirect addressing, and the contents of the memory bank select register 5 are set to an upper address MA9. It is composed of an upper address selection switching circuit 7 that selects the address to be outputted as MA8.

2 is a block diagram of the upper address selection switching circuit in FIG. 1, and FIG. 3 is a block diagram of the data memory to be accessed in FIG. 1.

As shown in FIG.
Pitsu) Contents of rO, rl and valid register selection register 6
and an AND gate 9 which takes the logical product of the output of the match judgment circuit 8 and each output of the memory bank select register 5.
and 10.

Further, as shown in FIG. 3, the data memory 13 has 102
It has a capacity of 4×4 bits and is composed of four memory banks 0 to 4 in units of 256×4 bits.

Next, the memory addressing operation will be explained in more detail using Figures 6 to 6.

FIG. 4 is a diagram showing the instruction code of the indirect addressing instruction in FIG. 1.

Assume that an instruction for exchanging memory with a microcomputer's 7 storage unit is an instruction code consisting of one byte as shown in FIG. 4 as an indirect addressing instruction. That is, when the lower 2 bits) r1°rO is OO, it indicates BC register indirect addressing, and when rl and rO are 01
indicates DE register indirect addressing, and r
When l and rO are lO, it is assumed that HL register indirect addressing is indicated. Therefore, when an indirect addressing instruction is executed, the lower address selection switching circuit 4 in FIG.
2 bits in the instruction code) Select one from HL register 1, DE register 2, or BC register 3 according to the rl and rO0 values, and output the contents as the lower 8 bits MAt to MAo of the memory address. do. The two bits (rl and ro) in this instruction code are further input to the upper address selection switching circuit 7.

On the other hand, before executing the indirect addressing instruction, predetermined values are set in the effective register selection register 6 and memory bank selection register 5 in advance. As mentioned above, the match determination circuit 8 of the upper address selection switching circuit 7 compares the contents of the effective register selection register 6 with the contents of rl and ro in the indirect addressing instruction code, and when they match, outputs a "1" level. For example, if 2 bits of the valid register selection register 6 are set to 10, when HL indirect addressing is performed, rl, r
Since O is 10, the match determination circuit 8 outputs "1".

FIGS. 5 and 6 are diagrams for explaining memory addressing in FIG. 1, respectively.

As shown in FIG.
0 to the memory address upper bit MA9. Since it is output as MA8, memory bank select register 5
It is possible to perform 7 dressings in the memory bank selected by the 8-bit contents MA7 to MAO of the HL register 1.

On the other hand, when DE indirect addressing is performed thereafter, the 2 bits rl and ro become 01, which does not match the content 10 of the valid register selection register 6, so the match determination circuit 8 outputs 0°.

That is, since the AND gates 9 and 1O output "0", the upper bits MA9 and MA
8 becomes 0, 0, and 7 dressings can be performed in memory bank 0 using the 8 bits of the contents of 2 in DE register 2.

Therefore, after performing an instruction to exchange the memory with the 7 cumulator using HL register indirect addressing for the memory bank selected by the memory bank select register 5, the contents of the memory bank select register 5 are left unchanged and the DB register is Executes an instruction to exchange the accumulator and memory using indirect addressing, and then returns to H again.
If an accumulator and memory exchange instruction is executed using L register indirect addressing, the contents of the memory in the memory bank specified by the memory bank select register 5 can be exchanged with the memory in the memory bank O, and during this time the contents of the memory bank select register 5 can be exchanged. There is no need to change the content number.

Further, in the above state, even when BC register indirect addressing is performed, the output of the match determination circuit 8 becomes 0°, and the inside of the memory node O is still accessed.

Furthermore, if the contents of the valid register selection register 6 are set to 01, in the case of DE register indirect addressing, 2 bits) rl and rO become Ol, so only in this case, the match judgment circuit 8 outputs l". 7 dressings can be performed on the memory bank selected by the select register 5.

Furthermore, in the case of HL register indirect addressing and BC register indirect addressing, memory node O is accessed.

Similarly, if the contents of the valid register selection register 6 are set to 00, 2
Since rl and rO become 00, the selected memory bank can be accessed only during this addressing.

Furthermore, when the content of the valid register selection register 6 is 11, all indirect addressing The memory bank selected by the memory bank select register 5 can be addressed.

Although not shown in FIG. 1, in the case of direct addressing, in which a memory address is directly specified by 8-bit data in an instruction word other than indirect addressing,
The contents of the memory bank select register 5 are always the upper address MA9. It may be configured to output to MA8.

FIG. 7 is a configuration diagram of an upper address selection switching circuit for explaining a second embodiment of the present invention.

As shown in FIG. 7, this embodiment is a partial modification of the configuration of the upper address selection switching circuit 7 in the first embodiment described above. That is, the AND game in Figure 2) 10
In this example, an inverter 11 and an OR gate 12 are used instead. As a result, when the output of the match determination circuit 8 is 0°, in the first embodiment, the upper address MA9. MA8
was 0.0 to select memory bank O, but in this embodiment, the upper address MA9. MA8 becomes 0, 1, and memory bank 1 is selected.

Therefore, in indirect addressing other than the indirect addressing specified by the effective register selection register 6, it is always possible to access the memory bank 1.

〔Effect of the invention〕

As explained above, the memory addressing method of the microcomputer of the present invention is based on register indirect addressing when data memory is divided into a plurality of memory banks, and in particular indirect addressing using different registers. By having indirect addressing selection means for enabling bank access, it is possible to exchange and transfer data between the memory bank selected by the memory bank select register and other memory banks, that is, between different memory banks. When performing a comparison operation, there is no need to frequently switch the memory bank designation, so there is an effect that both the number of program steps and the data processing time can be reduced. In particular, the effect is remarkable when the above data manipulation is repeated many times.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a memory addressing system of a microcomputer showing a first embodiment of the present invention, FIG. 2 is a block diagram of the upper address selection switching circuit in FIG. 1,
3 shows the country of data memory configuration to be accessed in FIG. 1, FIG. 4 shows the instruction code of the indirect addressing instruction in FIG. 1, and FIGS. FIG. 7 is a block diagram of an upper address selection switching circuit for explaining a second embodiment of the present invention. l...HL register, 2...DE register, 3...BC register, 4...lower address selection switching circuit, 5... Memory bank select register, 6... Valid register selection register, 7... Upper address selection switching circuit, 8
・・・・・・Concordance judgment circuit, 9゜10・・・・・・AN
D gate, 11... Inverter, 12...
...OR gate, 13...data memory.

Claims (1)

[Claims] A memory for a microcomputer, comprising a plurality of memory banks into which a memory space is divided, a memory bank select register for specifying one of the memory banks, and addressing means for indirectly specifying a memory address within the memory bank. In the addressing method, a plurality of indirect addressing registers, a lower address selection switching circuit that specifies one of the plurality of indirect addressing registers by an instruction code of an indirect addressing instruction and outputs it as part of a memory address; an effective register selection register that specifies indirect addressing that is valid for the memory bank specified by the memory bank select register, and the contents of the memory bank select register according to the contents of the effective register selection register and the type of the indirect addressing instruction. 1. A memory addressing system for a microcomputer, comprising: an upper address selection switching circuit for switching whether or not to output an upper memory address as an upper memory address.