JPH032944A - Increasing system for memory capacity - Google Patents

Abstract

PURPOSE:To increase the memory capacity without adding any new address bus and therefore to increase the memory capacity up to a level higher than the estimated value easily and in a simple constitution by attaining an access to a prescribed address set to an extension memory with use of a data bus set for writing and reading data. CONSTITUTION:An interface is applied to an extension memory 1 via a data bus 2, and an address is produced to give an access to a prescribed address set to the memory 1 with use of a data bus 2. This produced address is stored in an address data register 3, and the timing control is carried out for writing or reading the data via the bus 2 after the address is fixed. Therefore the prescribed address receives an access to the memory 1 with use of the bus 2 set for writing and reading data. As a result, the memory capacity can be increased without adding any new address bus.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for increasing the memory capacity of a data processing device such as a microcomputer that has a memory into which data is written by accessing a predetermined address.

[Conventional technology] Conventionally, in consideration of increasing memory capacity, a large memory area was created in advance, leaving a spare space, and this spare space was used to cope with the increase in memory capacity. Alternatively, if there is no room for spare space in the memory area, (1) a method of configuring a multi-mask (multi-CPU) system and increasing the memory capacity by providing memory to the second CPU;

■In the case of a single mask system, use two address buses.
A method is used in which a system is multiplexed and switched using a select signal to create a memory space twice as large as that of a single system address bus.

[Problems to be Solved by the Invention] However, the former method of increasing the memory capacity requires two CPUs and their peripheral circuits, making the system large-scale and increasing the equipment cost. In addition, with the latter method of increasing memory capacity, when designing the system, it is necessary to multiplex the address bus in advance in consideration of increasing the memory capacity, which may not be able to meet additional specifications. There is.

The present invention aims to solve the above-mentioned problems, and aims to provide a method for increasing the memory capacity that allows the memory capacity to be increased easily and with a simple configuration. .

[Means for Solving the Problems] In order to achieve the above object, the memory capacity increasing method of the present invention includes: (1) interfacing the additional memory with a data bus; (2) interfacing the additional memory with the data bus; The present invention is characterized in that a predetermined address is generated in order to access the address, and (1) after the address is determined, timing control for data writing or data reading with respect to the address is performed by the data bus.

[Function] In the method for increasing the memory capacity of the present invention described above, access to a predetermined address to the expanded memory is performed using the data bus for data writing and data reading. Memory capacity can be increased without adding additional .

[Embodiment of the Invention] A method for increasing the memory capacity as an embodiment of the present invention will be described below with reference to the drawings. Figure 1 is a circuit diagram showing the configuration of a device to which this method is applied. In Figure 1, 1 is an expanded/added memory, 2 is a memory 1 and a CP.
A data bus (in this embodiment, a 16-bit compatible data bus) is connected to U (not shown) and transmits both addresses and data, which will be described later.
Latch the predetermined address transmitted by bits D(15)-D(8) and write address data A(7)-A(0)
It is a memory address data register that outputs as
The lower 8 bits D(7) to D(0) of data bus 2 are used for transmitting write data or read data.

Also, 4 is the clock signal (CLK C1") from the CPU.
U) is a clock oscillator that outputs an asynchronous clock signal SL (or 81') of the same period, and in this embodiment,
A signal from a crystal oscillator that emits a 16 MHz signal is frequency-divided and used as an 8 MHz clock signal.

5.6 is a logic circuit that generates an ADRG signal for causing the register 3 to latch address data based on the PWR signal from the CPU and the memory address generation signal DAI; 7 is a clock signal from the clock oscillator 4 and the CPU.
This is a flip-flop that outputs a data write signal WR (Fl-Q) to the memory 1 from the Q terminal based on the PWR signal of the FF.

Furthermore, 12 is a clock signal from the clock oscillator 4;
PWR signal from CPU and Q of flip-flop 7
A flip-flop outputs from the Q terminal a signal F2-Q obtained by delaying the Fl-Q signal by one clock with respect to the clock signal from the tarock oscillator 4 based on the terminal output Fl-Q, and 13 is a PRD signal and memory read from the CPU. Address (AND circuit that takes AND with No. a DA3, 14
is an AND circuit that takes the AND of the F2-Q signal from the flip-flop 12 and the memory write address signal DA2;
Reference numeral 15 denotes an OR circuit which takes the logical sum of the outputs from the AND circuits 13 and 14 and outputs the result as a memory chip select signal C8.

Before explaining the operation of the device of this embodiment configured as described above, let us explain the normal case where the device has both an address bus and a data bus. ) and the operation when reading (RD) from memory will be explained.

Generally, when transmitting signals between the CPU and memory, the CPU outputs a memory address to the address bus, then outputs write data to the data bus, and then writes the data after confirming the data. This is done by outputting a signal.

On the other hand, reading data from the memory is performed by the CPU outputting a read address to the address bus, the memory outputting the data at the read address to the data bus, and after the data is determined, the CPU outputs a read signal.

In contrast to the general memory write and read operations described above, which use an address bus and a data bus, the method of this embodiment uses the circuit configuration shown in FIG. Addresses can be sent to the memory via a data bus, and data can be written and read using the same data bus, without the need for a data bus.

The point of this device is to avoid failure to satisfy the timing that the memory 1 has when data and addresses are simultaneously input to the memory 1 via the data bus 2. In normal memory timing, a chip must be selected after a predetermined memory address is determined, but when a predetermined memory address is generated by the data bus 2, the memory address becomes uncertain during chip selection.

Therefore, in this embodiment, by using the clock signal S1 or Sl' from the clock oscillator 4 to determine the timing of memory address determination and memory chip selection as described later, it is possible to interface with the CPU using only the data bus 2. There is.

Note that the clock oscillator 4 creates the timing of the write cycle of the memory 1, and each signal operates in synchronization with this clock oscillator 4. In the timing chart of Fig. 2.3, two types of clock signals, Sl and Sl', are depicted as clock signals from the clock oscillator 4, but this is
Since the PU CLK and the clock signal No. 8 from the clock oscillator 4 are asynchronous, the figures show cases in which the clock signal from the clock oscillator 4 leads and lags behind the CPU CLK, respectively.

Now, as shown in Figure 2, when writing data, the CP
U outputs a PWR signal, and data write signal WR is generated from the Q terminal of flip-flop 7 based on this PWR signal and clock signal S1.

Also, the output signal I from the Q terminal of the flip-flop 7;
1- Based on Q and clock signal Sl, a data write signal WR (Fl
-Q) is delayed by one clock to generate a signal F2-Q. Then, based on this signal F2-Q and memory write address signal DA2, a memory chip select signal C8 is generated in circuit 14.15.

Further, based on the memory address generation signal DAI and the PWR signal, the logic circuits 5 and 6 generate an ADRG signal for latching predetermined address data from the data bus 2 in the register 3.

As a result, first, predetermined address data from the data bus 2 is latched in the register 3, and after the address data is determined, the flip-flop 1 is delayed by one clock.
Memory 1 is chip-selected by the C8 signal at the Q terminal output F2-Q of No.2. Then, the data (W
-DATA) writing is performed at the timing of the rise of the data write signal WR, which is synchronized with the fall of the PWR signal in the T4 cycle.

On the other hand, when the CPU reads data from memory 1,
As shown in FIG. 3, the operation requires two cycles. That is, in one cycle, predetermined memory address data is set in the memory address data register 3, and in the next cycle, memory 1~ is performed. This is CP
This is because there is no address bus from U to the added memory L, and data bus 2 is used instead.

Also during data reading, the read cycle timing is created using the clock signal S1 or SL' from the clock oscillator 4. This clock signal S1 or S
L' is the same as in the data write operation to the memory 1.

As shown in FIG. 3, when reading data, the CPU first outputs the PWR signal, and based on the memory address generation signal DAI and the PWR signal, the logic circuits 5 and 6 generate the ADRG signal, and the register 3 data bus 2
Predetermined address data (read address) from is set. This address data continues to be output from the register 3 until the next memory address data is set.

The read address is determined in the first cycle.

Note that the above operation is the same as that at the time of data writing shown in FIG.

Next, the CPU shifts to a memory REET operation.

In other words, in the next cycle after the read address is determined, C
The PU outputs a PRD signal, and a memory chip select signal C8 is generated in a circuit 13.15 based on this PRD signal and a memory read address signal DA3.

Thereafter, data (R-DATA) is successively output to the data bus 2 at the timing of the rise of the chip select signal C8, which is synchronized with the rise of the PRD signal in the T4 cycle.

As described above, according to this embodiment, a predetermined address is accessed to the expanded memory 1 using the data bus 2 for data writing and data reading, and writing or reading is performed after the address is determined. Therefore, the memory capacity can be increased without adding a new address bus, and the capacity of the memory can be increased more easily than planned and with an extremely simple configuration.

In the above embodiment, the case where the data bus 2 supports 16 bits has been described, but the system of the present invention is not limited to this.

Furthermore, the method of the present invention can be applied, for example, to increasing or decreasing memory for storing teaching data in industrial robots.

[Effects of the Invention] As detailed above, according to the memory capacity increase method of the present invention, it is possible to access a predetermined address to the additional memory using the data bus for data writing and data reading. , the memory capacity can be increased without adding a new address bus, and the memory can be increased by four companies more than planned easily and with a simple configuration.

[Brief explanation of the drawing]

1 to 3 show a method for increasing memory capacity as an embodiment of the present invention. FIG. 1 is a circuit diagram showing the configuration of a device to which the wooden sword method is applied, and FIG. FIG. 3 is a timing chart for explaining a data write operation by the device, and FIG. 3 is a timing chart for explaining a data read operation by the device of this embodiment. In the figure, 1--memory, 2--data bus, 3--
Memory address data register, 4...clock oscillator, 5, 6...-logic circuit, 7...-flip-flop, 12...-flip-flop, 13.14...-AND circuit, 15...-OR circuit. Figure 2 T+ T2 T3 TW TWTW T4 Patent applicant Kobe Steel, Ltd.

Claims (1)

[Claims] In a data processing device having a memory that has a predetermined address and which writes data to or reads data from the address by accessing the address, when an additional memory is provided, interfacing the additional memory with a data bus; generating a predetermined address for accessing the additional memory using the data bus; and after determining the address, writing data to the address using the data bus; A method for increasing memory capacity characterized by controlling timing for loading or reading data.