JPH0330432U - - Google Patents
Info
- Publication number
- JPH0330432U JPH0330432U JP1989090463U JP9046389U JPH0330432U JP H0330432 U JPH0330432 U JP H0330432U JP 1989090463 U JP1989090463 U JP 1989090463U JP 9046389 U JP9046389 U JP 9046389U JP H0330432 U JPH0330432 U JP H0330432U
- Authority
- JP
- Japan
- Prior art keywords
- inner lead
- semiconductor device
- tip
- higher conductivity
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/015—Manufacture or treatment of bond wires
- H10W72/01515—Forming coatings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
- H10W72/07551—Controlling the environment, e.g. atmosphere composition or temperature characterised by changes in properties of the bond wires during the connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Wire Bonding (AREA)
Description
第１図は本考案の実施例を示す樹脂封止型半導
体装置の要部平面図、第２図は第１図のＡ−Ａ線
断面図、第３図は従来の製造途中のバイポーラリ
ニア半導体装置の平面図、第４図は従来の樹脂封
止型半導体装置の斜視図である。
１１……リードフレーム、１２……アイランド
、１３……半導体素子、１４……タイバー、１５
……半導体素子外部導出電極、１６……インナリ
ード、１６ａ……曲面、１７……金属細線、１９
……外部接続リード、２０……メツキエリア、２
１……金属層。
FIG. 1 is a plan view of the main parts of a resin-sealed semiconductor device showing an embodiment of the present invention, FIG. 2 is a cross-sectional view taken along line A-A in FIG. 1, and FIG. 3 is a conventional bipolar linear semiconductor in the process of being manufactured. A plan view of the device, and FIG. 4 is a perspective view of a conventional resin-sealed semiconductor device. 11... Lead frame, 12... Island, 13... Semiconductor element, 14... Tie bar, 15
...Semiconductor element external lead-out electrode, 16...Inner lead, 16a...Curved surface, 17...Metal thin wire, 19
...External connection lead, 20...Metsuki area, 2
1...Metal layer.
Claims (1)
装置において、 金属細線の接続部を除くインナリード先端部の
少なくとも側面に該インナリードの導電性より高
い導電性の金属層を形成したことを特徴とする半
導体装置。 (2) 請求項１記載の半導体装置において、前記
インナリード先端部の側面を曲面加工してなる半
導体装置。 (3) 請求項１記載の半導体装置において、前記
インナリード先端部の側面及び底面に該インナリ
ードの導電性より高い導電性の金属層を形成して
なる半導体装置。[Claims for Utility Model Registration] (1) In a semiconductor device equipped with a high-speed, high-frequency semiconductor element, at least the side surface of the tip of the inner lead, excluding the connecting portion of the thin metal wire, is made of a metal with higher conductivity than the inner lead. A semiconductor device characterized by forming layers. (2) The semiconductor device according to claim 1, wherein the side surface of the tip of the inner lead is processed into a curved surface. (3) The semiconductor device according to claim 1, wherein a metal layer having higher conductivity than the inner lead is formed on the side and bottom surfaces of the tip of the inner lead.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989090463U JPH0330432U (en) | 1989-08-02 | 1989-08-02 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989090463U JPH0330432U (en) | 1989-08-02 | 1989-08-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0330432U true JPH0330432U (en) | 1991-03-26 |
Family
ID=31639981
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989090463U Pending JPH0330432U (en) | 1989-08-02 | 1989-08-02 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0330432U (en) |
-
1989
- 1989-08-02 JP JP1989090463U patent/JPH0330432U/ja active Pending